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{ "id": 2226858, "url": "http://patchwork.ozlabs.org/api/covers/2226858/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260422204335.23116-1-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260422204335.23116-1-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-22T20:43:28", "name": "[v2,0/7] hw/arm/smmuv3-accel: Resolve AUTO properties", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260422204335.23116-1-nathanc@nvidia.com/mbox/", "series": [ { "id": 501105, "url": "http://patchwork.ozlabs.org/api/series/501105/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501105", "date": "2026-04-22T20:43:28", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501105/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2226858/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=qYX1XaeL;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=cG6NWlMFQzBKWua+kA1tMQQJUj1DhmKHKgR2tv4hpd8=;\n b=gnBt2pB5h3/WcwYu/r5iFB8kvjKG2BcYkWn2xgWf7JcqkyMPkeoJ0n1ckGnfShJ1bf7eoFSUiBBoPBzZ4C7i6u+vq58dP/cQvoR+q25YfB/rzeKoMTfKWBAIUQJ9bGfIcWDz0LKi2mFGlM4YKtzkuzs6oU8mhDsGSPEazUea7E9DLlbnxIkI7saXKC5lS3wIrIWNlhlEblgjD+DRB8lvvZCX1V4C5MCK1e6KFo93ApkYK0vRd/RJVUWP1efqfsWABZ5uj+vE+i5sfaWIcKFL+Fp0Dyz4toN2fhDjSzStCJggmuldofiUFga/f5J6gfzRWBD9zHpiD0SzXwZ+tUYy3w==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=cG6NWlMFQzBKWua+kA1tMQQJUj1DhmKHKgR2tv4hpd8=;\n b=qYX1XaeLnQ6xMnQtN4IKdPP6Eu+cZ745T+PkrksJhF6DCn7A7/gCa/pvqoEN7CSt07b+ni48YaxDWh4tdjiiaorqEz2ujrU11J3a550sj0a5B/kd3mVbSQHIho8LBG75GY/sHoeSEi4V9Z33n0+5SQEpkkKhzUi4Eza2wQAR+E6qzPdHDVd/iW2999R1XogYAFlMbX5DVY1W5KE8JQQtgFiRNw18xYWAR0erTP+OEY4KVhyFDg69jpBq1DV5b2FdJ5jAqRlTXnwMjpRkhQ/5RrAKTMhWYdoHJJ9xsTFjo08hpktGYnDuhhzZRLLn8C3GVPenRZrt/sj324S1kI8xXA==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Eric Auger <eric.auger@redhat.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH v2 0/7] hw/arm/smmuv3-accel: Resolve AUTO properties", "Date": "Wed, 22 Apr 2026 13:43:28 -0700", "Message-ID": "<20260422204335.23116-1-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ0PR03CA0212.namprd03.prod.outlook.com\n (2603:10b6:a03:39f::7) To CY3PR12MB9555.namprd12.prod.outlook.com\n (2603:10b6:930:10a::14)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY3PR12MB9555:EE_|SA1PR12MB7368:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d0eab06e-d49b-4e7e-eca0-08dea0afd88f", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n f67dLd7KIDHgEZMuHbGOpuLI2BJ0WunGknBUpJjFqGFadwW99a8Tnp18Ry6Y9Rq3LdowI1SSVNTUci2LU+ooM5QJnG9p4ikpzRs0oSgQ73aJAmel0p/9oq44+gCIeCEYLCZmLFwjuv8EbUFFqDPdZt5SUaFZ4e9bnFyO+o7T6aqQvn+zg1S8qXx6EuWZWS9J7xyv+YNelunioSkCSa9E2I7J9Jf/jMsI5WvQJP2FZui99UgbiUHtIVMxeTr+vPBhAA5RZYNe5hiqCscqvIERIdMjH1FaEwDYUyyJargqVPPiGuVceNwoEjKA0cX3Ul+aAg5IXnCUDDFCUDNkBgBMlMqZR+lzRJfah0PQh5N9AKZ0UgNJ0C6Z5vaDoPC+xs1H0GgM0rkNllEKn5dIWiWtMgDp7VKa6q3f69tarkF+gqI+cUhYujmvzSw2AG+Yw8d7gxSv0xPxqTzPGutL3yjZ+65WwgH91leBX3CX/27XWW50Zv8WM6eniFRYKg4DJDQK9oZcEd/Pjyn8My+xBMMeQf1YFyAPHmnEpFdtMvIT8EgjAvEAe6ZeQJOFPr/23mCQsPubU4jNLFcqlreq6vpTrxPAFvyTGSG3PF/kOioK+Muxzn2/9T/3ZgiWfs5kTDM4c+UQguRvHWZUU2/4XUN1jgidUUrxHSwwqKKU2/ZrEIHa2vwgXYThPrtOcrM5d89StHz6r/qn+2hzVxZ2qGtvBzAZwNQoK1eBL420gw5WmQr9ksU4PHV2VwyQCyA9+SV7", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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This is dependent on the series [0] for\nchanging these property types to accept 'auto' values.\n\nAccelerated SMMUv3 Address Translation Services support is derived from\nIDR0, Range Invalidation support is derived from IDR3, Substream ID\nsize is derived from IDR1, and output address space is derived from\nIDR5.\n\nThe default values are set to 'auto' for all properties. If accel=off\nand the values are set to 'auto' or are omitted and resolve to 'auto',\nthe default property values defined in smmuv3_init_id_regs() for OAS\nand RIL will remain unchanged, while SSIDSIZE and ATS values will\nremain initialized at 0.\n\nA complete branch can be found here:\nhttps://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-resolve-v2\n\nPlease take a look and let me know your feedback.\n\nThanks,\nNathan\n\n[0] https://lore.kernel.org/qemu-arm/20260323182454.1416110-1-nathanc@nvidia.com/\n\nExample usage:\nqemu-system-aarch64 \\\n -object iommufd,id=iommufd0 \\\n -machine virt,accel=kvm,gic-version=3,ras=on,highmem-mmio-size=4T \\\n -cpu host -smp cpus=4 -m size=16G -nographic \\\n -object memory-backend-ram,size=16G,id=m0 \\\n -numa node,memdev=m0,cpus=0-3,nodeid=0 \\\n -numa node,nodeid=1 -numa node,nodeid=2 -numa node,nodeid=3 -numa node,nodeid=4 \\\n -numa node,nodeid=5 -numa node,nodeid=6 -numa node,nodeid=7 -numa node,nodeid=8 \\\n -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0,numa_node=0 \\\n -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1,accel=on,ats=auto,ssidsize=auto,ril=auto,oas=auto \\\n -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,io-reserve=0 \\\n -device vfio-pci-nohotplug,host=0009:06:00.0,bus=pcie.port1,rombar=0,id=dev0,iommufd=iommufd0,ats=auto \\\n -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=1 \\\n -object acpi-generic-initiator,id=gi1,pci-dev=dev0,node=2 \\\n -object acpi-generic-initiator,id=gi2,pci-dev=dev0,node=3 \\\n -object acpi-generic-initiator,id=gi3,pci-dev=dev0,node=4 \\\n -object acpi-generic-initiator,id=gi4,pci-dev=dev0,node=5 \\\n -object acpi-generic-initiator,id=gi5,pci-dev=dev0,node=6 \\\n -object acpi-generic-initiator,id=gi6,pci-dev=dev0,node=7 \\\n -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=8 \\\n -bios /usr/share/AAVMF/AAVMF_CODE.fd \\\n -device nvme,drive=nvme0,serial=deadbeaf1,bus=pcie.0 \\\n -drive file=/var/lib/libvirt/images/guest.qcow2,index=0,media=disk,format=qcow2,if=none,id=nvme0 \\\n -device e1000,romfile=/usr/local/share/qemu/efi-e1000.rom,netdev=net0,bus=pcie.0 \\\n -netdev user,id=net0,hostfwd=tcp::5558-:22,hostfwd=tcp::5586-:5586\n\nTesting:\nBasic sanity testing was performed on an NVIDIA Grace platform with GPU\ndevice assignment and running CUDA test apps on the guest. Observed the\nfeature properties being set based on host IOMMU capabilities.\nVerified that the VM boot will fail without a cold-plugged device, and\nthat a hot-plugged device re-uses the resolved values from the initial\ncold-plug. Additional testing and feedback are welcome.\n\nNathan Chen (7):\n hw/arm/smmuv3-accel: Add helper for resolving auto parameters\n hw/arm/smmuv3-accel: Implement \"auto\" value for \"ats\"\n hw/arm/smmuv3-accel: Implement \"auto\" value for \"ril\"\n hw/arm/smmuv3-accel: Implement \"auto\" value for \"ssidsize\"\n hw/arm/smmuv3-accel: Implement \"auto\" value for \"oas\"\n hw/arm/smmuv3: Set default ats, ril, ssidsize, oas to auto\n qemu-options.hx: Support \"auto\" for accel SMMUv3 properties\n\n hw/arm/smmuv3-accel.c | 80 ++++++++++++++++++++++++++++++++++++++++-\n hw/arm/smmuv3-accel.h | 2 ++\n hw/arm/smmuv3.c | 63 +++++++++++++++-----------------\n hw/core/machine.c | 8 +++++\n include/hw/arm/smmuv3.h | 2 ++\n qemu-options.hx | 33 +++++++++++------\n 6 files changed, 143 insertions(+), 45 deletions(-)" }