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{ "id": 2225829, "url": "http://patchwork.ozlabs.org/api/covers/2225829/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260421162912.3295598-1-jim.shu@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421162912.3295598-1-jim.shu@sifive.com>", "list_archive_url": null, "date": "2026-04-21T16:29:07", "name": "[v2,0/5] Defer the IOMMU translation and support access_type", "submitter": { "id": 83153, "url": "http://patchwork.ozlabs.org/api/people/83153/?format=api", "name": "Jim Shu", "email": "jim.shu@sifive.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260421162912.3295598-1-jim.shu@sifive.com/mbox/", "series": [ { "id": 500851, "url": "http://patchwork.ozlabs.org/api/series/500851/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500851", "date": "2026-04-21T16:29:09", "name": "Defer the IOMMU translation and support access_type", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500851/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2225829/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=LJB5ukNq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Iglesias\" <edgar.iglesias@gmail.com>,\n Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, Stafford Horne <shorne@gmail.com>,\n Nicholas Piggin <npiggin@gmail.com>, Chinmay Rath <rathc@linux.ibm.com>,\n Glenn Miles <milesg@linux.ibm.com>, Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>,\n Yoshinori Sato <yoshinori.sato@nifty.com>,\n Ilya Leoshkevich <iii@linux.ibm.com>, David Hildenbrand <david@kernel.org>,\n Cornelia Huck <cohuck@redhat.com>, Eric Farman <farman@linux.ibm.com>,\n Matthew Rosato <mjrosato@linux.ibm.com>,\n Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,\n Artyom Tarasenko <atar4qemu@gmail.com>,\n Bastian Koppelmann <kbastian@rumtueddeln.de>,\n Max Filippov <jcmvbkbc@gmail.com>,\n qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs),\n qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu <jim.shu@sifive.com>", "Subject": "[PATCH v2 0/5] Defer the IOMMU translation and support access_type", "Date": "Wed, 22 Apr 2026 00:29:07 +0800", "Message-ID": "<20260421162912.3295598-1-jim.shu@sifive.com>", "X-Mailer": "git-send-email 2.43.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::1033;\n envelope-from=jim.shu@sifive.com; helo=mail-pj1-x1033.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Note: v1 title is \"accel/tcg: Pass the access_type to IOMMUMemoryRegion\"\n\nIncoming security protection devices feature more complex IOMMUMemoryRegion\nimplementation in the CPU path than ARM MPC device. For example,\nRISC-V wgChecker [1] may permit the access with only RO/WO permissions.\nConsequently, the IOMMUMemoryRegion could return different sections for\nread & write access.\n\nTo support such IOMMUMemoryRegion behavior in the CPU path, the design\nof IOMMU translation must be updated:\n\n1. address_space_translate*() must now pass the access_type to\n IOMMUMemoryRegion.\n2. Since IOMMU translation results are too complex to be fully stored\n in the CPU TLB. we will defer the translation until the actual access\n occurs. Also, TLB is allowed to store the untranslated IOMMU region.\n\nTo implement deferred IOMMU translation, this patchset introduces the\nfollowing changes:\n\n1. tlb_set_page_full() no longer translates the IOMMU region\n immediately. Instead, it stores the untranslated region directly in\n the TLB. A new slow-path flag, TLB_IOMMU, is introduced to force\n access into the slow path when a region has not yet been translated\n in the TLB entry.\n\n2. When the CPU utilizes a TLB entry in the slow path, it should perform\n the lazy IOMMU translation of the access_type first. The resulting\n translated region and access type are stored in CPUTLBEntryFull.\n Since the slow path always performs lazy translation first, we can\n switch the CPUTLBEntryFull content to the correct access type before\n use.\n\n3. To accelerate memory access in the fast path, lazy translation can\n update the addend of the CPUTLBEntry when translating the region to a\n host memory region. We restrict the IOMMU region to have a single\n non-zero 'addend' across all permissions. If a second 'addend' is\n present for a CPUTLBEntry, QEMU will trigger an assertion. This\n limitation is sufficient for security devices, as their \"secondary\"\n region is typically an IO region used to emulate device error\n handling when access is rejected.\n\n4. To support non-slow TLB flags, lazy translation can update the TLB\n flags in the 'addr_idx' of the CPUTLBEntry. Lazy translation only\n updates the flags for the permissions specified in @prot. This\n ensures that each access_type of a translated region to maintains\n independent TLB flags. For example, TLB_DIRTY of memory region will\n not be \"polluted\" from other permission that translated to different\n region.\n\nBoth RISC-V wgChecker [1] and RISC-V IOPMP [2] devices require this\nfeature.\n\n[1] RISC-V WG:\nhttps://patchew.org/QEMU/20251021155548.584543-1-jim.shu@sifive.com/\n[2] RISC-V IOPMP:\nhttps://patchew.org/QEMU/20250312093735.1517740-1-ethan84@andestech.com/\n\nChanged since v1:\n- Remove the ping-pong TLB entry behavior. Instead, defer the IOMMU\n translation until actual access in the CPU path. Provide a IOMMU\n lazy translation function with the special handling of 'addend'\n and 'addr_idx' fields of CPUTLBEntry.\n- Fix the checkpatch warning.\n\n\nJim Shu (5):\n accel/tcg: Pass access_type as an argument of tlb_set_page*()\n accel/tcg: address_space_translate*() will pass the correct\n iommu_flags\n accel/tcg: Provide early AS translate function\n accel/tcg: Add IOMMU lazy translation function\n accel/tcg: Support IOMMU lazy translation in CPU TLB\n\n accel/tcg/cputlb.c | 247 +++++++++++++++++++++++++--\n include/accel/tcg/iommu.h | 17 +-\n include/exec/cputlb.h | 11 +-\n include/exec/tlb-flags.h | 4 +-\n include/hw/core/cpu.h | 15 ++\n system/physmem.c | 60 ++++++-\n target/alpha/helper.c | 2 +-\n target/avr/helper.c | 3 +-\n target/hppa/mem_helper.c | 1 -\n target/i386/tcg/system/excp_helper.c | 3 +-\n target/loongarch/tcg/tlb_helper.c | 2 +-\n target/m68k/helper.c | 10 +-\n target/microblaze/helper.c | 8 +-\n target/mips/tcg/system/tlb_helper.c | 4 +-\n target/or1k/mmu.c | 2 +-\n target/ppc/mmu_helper.c | 2 +-\n target/riscv/cpu_helper.c | 2 +-\n target/rx/cpu.c | 3 +-\n target/s390x/tcg/excp_helper.c | 2 +-\n target/sh4/helper.c | 3 +-\n target/sparc/mmu_helper.c | 6 +-\n target/tricore/helper.c | 2 +-\n target/xtensa/helper.c | 3 +-\n 23 files changed, 354 insertions(+), 58 deletions(-)" }