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{ "id": 2225504, "url": "http://patchwork.ozlabs.org/api/covers/2225504/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260421053140.752059-1-joel@jms.id.au/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421053140.752059-1-joel@jms.id.au>", "list_archive_url": null, "date": "2026-04-21T05:31:25", "name": "[v3,00/13] hw/riscv: Add the Tenstorrent Atlantis machine", "submitter": { "id": 48628, "url": "http://patchwork.ozlabs.org/api/people/48628/?format=api", "name": "Joel Stanley", "email": "joel@jms.id.au" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260421053140.752059-1-joel@jms.id.au/mbox/", "series": [ { "id": 500733, "url": "http://patchwork.ozlabs.org/api/series/500733/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500733", "date": "2026-04-21T05:31:26", "name": "hw/riscv: Add the Tenstorrent Atlantis machine", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500733/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2225504/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=CajuKtje;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g09zr4wCcz1yCv\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 21 Apr 2026 15:35:20 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wF3jV-0000OR-F5; Tue, 21 Apr 2026 01:33:13 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wF3jQ-0000IY-DC\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:08 -0400", "from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <joel.stan@gmail.com>)\n id 1wF3jN-0004NP-2u\n for qemu-devel@nongnu.org; Tue, 21 Apr 2026 01:33:07 -0400", "by mail-pj1-x1035.google.com with SMTP id\n 98e67ed59e1d1-3567e2b4159so2538492a91.0\n for <qemu-devel@nongnu.org>; Mon, 20 Apr 2026 22:33:04 -0700 (PDT)", "from donnager-debian.. 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There have been a bunch of\nimprovements made since the last posting:\n\n - Narrow the AIA refactor, virt-specific code stays in virt.c rather\n than moving to aia.c\n - riscv_boot_info_init must be called before\n riscv_find_and_load_firmware in sifive_u\n - Fix fw_cfg_init_mem_dma API change in the Atlantis machine\n - Fix create_fdt_pmu copying RISCVCPUs by value\n - Fix memory leaks in PCIe DT string allocation\n - Fix functional test file paths and remove unused import\n - Add trace events to the DesignWare I2C driver\n - Add device tree clock to I2C integration\n - Remove unused MachineState argument from halting payload helper\n - Remove unused platform_bus from Atlantis machine\n - Use HWADDR_PRIX consistently\n\nOriginal cover letter:\n\nIntroducing Tenstorrent Atlantis!\n\n The Tenstorrent Atlantis platform is a collaboration between Tenstorrent\n and CoreLab Technology. It is based on the Atlantis SoC, which includes\n the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.\n\n The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant\n RISC-V CPU.\n\nThis initial series adds the base machine support including:\n\n - AIA (Advanced Interrupt Architecture) support\n - PCIe controller and DesignWare I2C integration\n - Serial console and device tree generation\n - Functional tests for OpenSBI+Linux boot\n\nChris Rauer (1):\n hw/i2c: Add designware i2c controller\n\nJoel Stanley (5):\n hw/riscv/virt: Move AIA initialisation to helper file\n hw/riscv/aia: Provide number of irq sources\n hw/riscv: Add Tenstorrent Atlantis machine\n hw/riscv/atlantis: Integrate i2c buses\n hw/riscv/atlantis: Add some i2c peripherals\n\nNicholas Piggin (7):\n hw/riscv/boot: Describe discontiguous memory in boot_info\n hw/riscv/boot: Account for discontiguous memory when loading firmware\n hw/riscv/boot: Provide a simple halting payload\n target/riscv: tt-ascalon: Enable Zkr extension\n target/riscv: tt-ascalon: Add Svadu extension\n hw/riscv/atlantis: Add PCIe controller\n tests/functional/riscv64: Add tt-atlantis tests\n\n MAINTAINERS | 20 +\n docs/system/riscv/tt_atlantis.rst | 38 +\n docs/system/target-riscv.rst | 1 +\n hw/riscv/aia.h | 25 +\n include/hw/i2c/designware_i2c.h | 101 ++\n include/hw/riscv/boot.h | 13 +-\n include/hw/riscv/tt_atlantis.h | 92 ++\n include/hw/riscv/virt.h | 2 +-\n hw/i2c/designware_i2c.c | 818 ++++++++++++++++\n hw/riscv/aia.c | 93 ++\n hw/riscv/boot.c | 49 +-\n hw/riscv/microchip_pfsoc.c | 6 +-\n hw/riscv/opentitan.c | 6 +-\n hw/riscv/shakti_c.c | 6 +-\n hw/riscv/sifive_u.c | 6 +-\n hw/riscv/spike.c | 6 +-\n hw/riscv/tt_atlantis.c | 932 +++++++++++++++++++\n hw/riscv/virt-acpi-build.c | 27 +-\n hw/riscv/virt.c | 96 +-\n hw/riscv/xiangshan_kmh.c | 6 +-\n target/riscv/cpu.c | 2 +-\n hw/i2c/Kconfig | 4 +\n hw/i2c/meson.build | 1 +\n hw/i2c/trace-events | 4 +\n hw/riscv/Kconfig | 20 +\n hw/riscv/meson.build | 3 +-\n tests/functional/riscv64/meson.build | 1 +\n tests/functional/riscv64/test_opensbi.py | 4 +\n tests/functional/riscv64/test_tt_atlantis.py | 63 ++\n 29 files changed, 2337 insertions(+), 108 deletions(-)\n create mode 100644 docs/system/riscv/tt_atlantis.rst\n create mode 100644 hw/riscv/aia.h\n create mode 100644 include/hw/i2c/designware_i2c.h\n create mode 100644 include/hw/riscv/tt_atlantis.h\n create mode 100644 hw/i2c/designware_i2c.c\n create mode 100644 hw/riscv/aia.c\n create mode 100644 hw/riscv/tt_atlantis.c\n create mode 100755 tests/functional/riscv64/test_tt_atlantis.py" }