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{ "id": 2224146, "url": "http://patchwork.ozlabs.org/api/covers/2224146/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/cover/cover.1776381841.git.nicolinc@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<cover.1776381841.git.nicolinc@nvidia.com>", "list_archive_url": null, "date": "2026-04-16T23:28:29", "name": "[v3,00/11] iommu/arm-smmu-v3: Quarantine device upon ATC invalidation timeout", "submitter": { "id": 82183, "url": "http://patchwork.ozlabs.org/api/people/82183/?format=api", "name": "Nicolin Chen", "email": "nicolinc@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/cover/cover.1776381841.git.nicolinc@nvidia.com/mbox/", "series": [ { "id": 500217, "url": "http://patchwork.ozlabs.org/api/series/500217/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=500217", "date": "2026-04-16T23:28:31", "name": "iommu/arm-smmu-v3: Quarantine device upon ATC invalidation timeout", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/500217/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2224146/comments/", "headers": { "Return-Path": "\n <linux-pci+bounces-52660-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=iFDoX1th;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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pr=C", "From": "Nicolin Chen <nicolinc@nvidia.com>", "To": "Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, \"Joerg\n Roedel\" <joro@8bytes.org>, Bjorn Helgaas <bhelgaas@google.com>, \"Jason\n Gunthorpe\" <jgg@nvidia.com>", "CC": "\"Rafael J . Wysocki\" <rafael@kernel.org>, Len Brown <lenb@kernel.org>,\n\tPranjal Shrivastava <praan@google.com>, Mostafa Saleh <smostafa@google.com>,\n\tLu Baolu <baolu.lu@linux.intel.com>, Kevin Tian <kevin.tian@intel.com>,\n\t<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,\n\t<linux-kernel@vger.kernel.org>, <linux-acpi@vger.kernel.org>,\n\t<linux-pci@vger.kernel.org>, <vsethi@nvidia.com>, Shuai Xue\n\t<xueshuai@linux.alibaba.com>", "Subject": "[PATCH v3 00/11] iommu/arm-smmu-v3: Quarantine device upon ATC\n invalidation timeout", "Date": "Thu, 16 Apr 2026 16:28:29 -0700", "Message-ID": "<cover.1776381841.git.nicolinc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF00012E7F:EE_|SA1PR12MB7270:EE_", "X-MS-Office365-Filtering-Correlation-Id": "930ae050-fa76-416e-2f98-08de9c0ff427", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700016|13003099007|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\t66CcvihgFq6SU9VIbIo/LssZOYa11c25RZcB1idNpykOBDzjrXk4KB/du+DzN2O3jv8znEGlgcyfGRDQijMvPMNZFVBWmG6dEyleb6io5iKOG0c9+aXis8JGCznlM4xmLqt3b0EhvD42ucM+uJ0QO1OsIP6pR8c9tcZe3GqOXZRAsIUHN2D9b3i42kjeBCCOEsdwk//HOeAp+HC76K9FAmnyZnnWbeLGXUT4uSf2sEIrbL3PpIG6VNL7nWUhkgOsBicNsXL/Ya5BgFqG3gie0BFUviAGaCQgMsazoT51J7aRBA/1g9vMgAryi2+YGDYgBG2gVTUCS0xe2VeWnoWys64RPNqrwIXgyACYANK4bq2bCAd+AbjJQfB44HY0EhxUtQsNjF/wFNiJjBgsbGCIuytGq0ECb+ThANu7EokA4dvoHvt0ZrtBn4WyuRM04NtQB8JFp5zAbdXymrAPmYsbMC2dc9rdPinw7o8UDwJKqZOqN0Zak8IT7flb0dS9eLUq/E1UFOd4EivdYaIpGWVz4aPk843iYLk9/Jgl9Tc3Tdi7uN0AdQh84ZZqkmB9ooYNwVwgwvrHWhOXq6sGDlZ4/yxdQpLhOjiy3h+8Joc7Gan2/L/FcjzM6fxUCJZ+ul+AS31Zg6zHVQ3d4McBqLNa1pW4KCh5I46WsaXMUFHX0VpMH9gsBZ/WUGt8Cgp7Sdph2H+CBpmRvlIAX5fX07ZE0kghnFb/pjbvKewQasuOBjRmUMZxPjbeJdUx8OhMmQD5WqAK9WTWjbN/Y06UMalSrQ==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700016)(13003099007)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tU64+25db3RyvvqyyMeQvSWkZDe4+2sOpAxbY6w7B8kEedvJXoG07S8j/j6zq8iu91UAmIXGXeFLP9iV0OCjNEcAOmfN1/DzH/s8mrtqcS/iUeozZ7mT7XK5Z9EZ4kwLGkvvO5yX6hcUoafi5GgATOIKpAH9Lcxtv1o8WwhpguT+EqvVUUWHYNmIT/T9neCzet8CVdc5xI41sBzdECdibUruSfrgsl31eb6t+wyqpG+S0wC2jAYMTLY6EHnER4/icAWleo+w0bnMo4uvqwWXO5Sb6swhYCvNYS4NFadz6IYRh/gP1+ewwt/y7rUpwTwJsPTwJhvlyFo3JS4kdWR80YvgncaswuPikDxRwdy5jBsv7Wc0yv0S0Cc0TlKwD7Q4W1JQtGIOIIgM26v63nIrkiQ0VZsrdQWG0n+SCKXWnqrhD6/brF/TSzpg5mK+oh4FS", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Apr 2026 23:29:06.6767\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 930ae050-fa76-416e-2f98-08de9c0ff427", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCO1PEPF00012E7F.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB7270" }, "content": "Hi all,\n\nThis series addresses a critical vulnerability and stability issue where an\nunresponsive PCIe device failing to process ATC (Address Translation Cache)\ninvalidation requests leads to silent data corruption and continuous SMMU\nCMDQ error spam.\n\n[ As Jason pointed out, because this series fundamentally introduces a new\n RAS feature to quarantine and recover from hardware faults and relies on\n a recently accepted SMMU driver rework, it is not treated as a standard\n bug fix. Thus, none of the patches here carries a \"Fixes\" tag. ]\n\nCurrently, when an ATC invalidation times out, the SMMUv3 driver skips the\nCMDQ_ERR_CERROR_ATC_INV_IDX error. This leaves the device's ATS cache state\ndesynchronized from the SMMU: the device cache may retain stale ATC entries\nfor memory pages that the OS has already reclaimed and reassigned, creating\na direct vector for data corruption. Furthermore, the driver might continue\nissuing ATC_INV commands, resulting in constant CMDQ errors:\n unexpected global error reported (0x00000001), this could be serious\n CMDQ error (cons 0x0302bb84): ATC invalidate timeout\n unexpected global error reported (0x00000001), this could be serious\n CMDQ error (cons 0x0302bb88): ATC invalidate timeout\n unexpected global error reported (0x00000001), this could be serious\n CMDQ error (cons 0x0302bb8c): ATC invalidate timeout\n ...\n\nTo resolve this, introduce a mechanism to quarantine a broken device in the\nSMMUv3 driver and the IOMMU core. To achieve this, add preparatory changes:\n - Tighten the semantics of pci_dev_reset_iommu_done() that is now strictly\n called only upon a successful hardware reset\n - Introduce a reset_device_done op, allowing the core to signal the driver\n when the physical hardware has been cleanly recovered (e.g., via AER or\n a manual reset) so the quarantine can be lifted\n - Utilize a per-group_device WQ via an iommu_report_device_broken() helper\n\nOn the SMMUv3 driver side, retry the timedout ATC_INV batch to identify the\nfaulty device(s) via an atc_sync_timeouts tracker. Perform a surgical STE\nupdate and flag the ATS as broken to reject further ATS/ATC requests at the\nhardware level and suppress further timeout spam.\n\nThis is on Github:\nhttps://github.com/nicolinc/iommufd/commits/smmuv3_atc_timeout-v3\n\nNote that patches are rebased on bug-fix under review:\nhttps://lore.kernel.org/all/20260407194644.171304-1-nicolinc@nvidia.com/\n\nChangelog\nv3:\n * Rebase on arm/smmu/updates branch + bug fix\n * Update commit messages and inline comments\n * [iommu] Drop unnecessary ops validation\n * [iommu] Add missed function stub when !CONFIG_IOMMU_API\n * [iommu] Change iommu_report_device_broken() to per gdev\n * [iommu] Separate quarantine from pci_dev_reset_prepare()\n * [iommu] Check reset failure in pci_dev_reset_iommu_done()\n * [smmuv3] Fix STE update with try_cmpxchg64()\n * [smmuv3] Fix \"continue\" bug when skipping ATC commands\n * [smmuv3] Replace atomic_t prod_err with a lockless bitmap\n * [smmuv3] Drop master->invs_domain; disable ATS per-master directly\n * [smmuv3] Return -EIO for ATC timeout v.s. -ETIMEDOUT for poll timeout\n * [smmuv3] Replace INV_TYPE_ATS_DISABLED with per-master ats_broken flag\nv2:\n https://lore.kernel.org/all/cover.1773774441.git.nicolinc@nvidia.com/\n * Rebase on arm_smmu_invs-v13 series [0]\n * Bisect batched atc invalidation commands\n * Drop the direct pci_reset_function() call\n * Move the work queue from SMMUv3 to the core\n * Proceed a surgical STE update to disable EATS\n * Wait for pci_dev_reset_iommu_done() to signal a recovery\nv1:\n https://lore.kernel.org/all/cover.1772686998.git.nicolinc@nvidia.com/\n\n[0] https://lore.kernel.org/all/cover.1773733797.git.nicolinc@nvidia.com/\n\nThanks\nNicolin\n\nNicolin Chen (11):\n PCI: Propagate FLR return values to callers\n iommu: Pass in reset result to pci_dev_reset_iommu_done()\n iommu: Add reset_device_done callback for hardware fault recovery\n iommu: Add __iommu_group_block_device helper\n iommu: Change group->devices to RCU-protected list\n iommu: Defer __iommu_group_free_device() to be outside group->mutex\n iommu: Add iommu_report_device_broken() to quarantine a broken device\n iommu/arm-smmu-v3: Mark ATC invalidate timeouts via lockless bitmap\n iommu/arm-smmu-v3: Replace smmu with master in arm_smmu_inv\n iommu/arm-smmu-v3: Introduce master->ats_broken flag\n iommu/arm-smmu-v3: Block ATS upon an ATC invalidation timeout\n\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 +-\n include/linux/iommu.h | 15 +-\n .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 34 ++-\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 193 +++++++++++-\n drivers/iommu/iommu.c | 284 ++++++++++++++----\n drivers/pci/pci-acpi.c | 2 +-\n drivers/pci/pci.c | 10 +-\n drivers/pci/quirks.c | 24 +-\n 8 files changed, 454 insertions(+), 112 deletions(-)" }