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{ "id": 2223907, "url": "http://patchwork.ozlabs.org/api/covers/2223907/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1776339451.git.matheus.bernardino@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<cover.1776339451.git.matheus.bernardino@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-16T11:38:49", "name": "[v5,00/16] hexagon: add missing HVX float instructions", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1776339451.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 500137, "url": "http://patchwork.ozlabs.org/api/series/500137/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500137", "date": "2026-04-16T11:38:50", "name": "hexagon: add missing HVX float instructions", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/500137/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2223907/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=HBEIFCAy;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com 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DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This patchset adds 59 HVX floating point instructions from Hexagon\nrevisions v68 and v73 that were missing in qemu. Tests are also added at\nthe end.\n\nv4: https://lore.kernel.org/qemu-devel/cover.1775843299.git.matheus.bernardino@oss.qualcomm.com/\nv3: https://lore.kernel.org/qemu-devel/cover.1775665981.git.matheus.bernardino@oss.qualcomm.com/\nv2: https://lore.kernel.org/qemu-devel/cover.1775122853.git.matheus.bernardino@oss.qualcomm.com/\nv1: https://lore.kernel.org/qemu-devel/cover.1774271525.git.matheus.bernardino@oss.qualcomm.com/\n\nChanges in v5:\n\t- patch 11: fixed copy-and-paste error (s/vmax/vmin)\n\t- patch 16: replaced float16 value for BF_* constants for\n\t clearity\n\n\nBrian Cain (1):\n tests/docker: Update hexagon cross toolchain to 22.1.0\n\nMatheus Tavares Bernardino (15):\n target/hexagon: fix incorrect/too-permissive HVX encodings\n target/hexagon/cpu: add HVX IEEE FP extension\n hexagon: group cpu configurations in their own struct\n hexagon: print info on \"-d in_asm\" for disabled IEEE FP instructions\n target/hexagon: add v68 HVX IEEE float arithmetic insns\n target/hexagon: add v68 HVX IEEE float min/max insns\n target/hexagon: add v68 HVX IEEE float misc insns\n target/hexagon: add v68 HVX IEEE float conversion insns\n target/hexagon: add v68 HVX IEEE float compare insns\n target/hexagon: add v73 HVX IEEE bfloat16 insns\n tests/hexagon: add tests for v68 HVX IEEE float arithmetics\n tests/hexagon: add tests for v68 HVX IEEE float min/max\n tests/hexagon: add tests for v68 HVX IEEE float conversions\n tests/hexagon: add tests for v68 HVX IEEE float comparisons\n tests/hexagon: add tests for HVX bfloat\n\n target/hexagon/cpu.h | 10 +-\n target/hexagon/cpu_bits.h | 10 +-\n target/hexagon/mmvec/hvx_ieee_fp.h | 69 ++++\n target/hexagon/mmvec/macros.h | 8 +\n target/hexagon/mmvec/mmvec.h | 3 +\n target/hexagon/printinsn.h | 2 +-\n target/hexagon/translate.h | 1 +\n tests/tcg/hexagon/hex_test.h | 32 ++\n tests/tcg/hexagon/hvx_misc.h | 73 ++++\n target/hexagon/attribs_def.h.inc | 9 +\n disas/hexagon.c | 3 +-\n target/hexagon/arch.c | 8 +\n target/hexagon/cpu.c | 18 +-\n target/hexagon/decode.c | 4 +-\n target/hexagon/mmvec/hvx_ieee_fp.c | 137 +++++++\n target/hexagon/printinsn.c | 7 +-\n target/hexagon/translate.c | 5 +-\n tests/tcg/hexagon/fp_hvx.c | 226 +++++++++++\n tests/tcg/hexagon/fp_hvx_cmp.c | 275 +++++++++++++\n tests/tcg/hexagon/fp_hvx_cvt.c | 219 +++++++++++\n tests/tcg/hexagon/fp_hvx_disabled.c | 57 +++\n target/hexagon/gen_tcg_funcs.py | 11 +\n target/hexagon/hex_common.py | 27 ++\n target/hexagon/imported/mmvec/encode_ext.def | 126 ++++--\n target/hexagon/imported/mmvec/ext.idef | 369 +++++++++++++++++-\n target/hexagon/meson.build | 1 +\n .../dockerfiles/debian-hexagon-cross.docker | 10 +-\n tests/tcg/hexagon/Makefile.target | 14 +\n 28 files changed, 1686 insertions(+), 48 deletions(-)\n create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.h\n create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.c\n create mode 100644 tests/tcg/hexagon/fp_hvx.c\n create mode 100644 tests/tcg/hexagon/fp_hvx_cmp.c\n create mode 100644 tests/tcg/hexagon/fp_hvx_cvt.c\n create mode 100644 tests/tcg/hexagon/fp_hvx_disabled.c\n\nRange-diff against v4:\n 1: 1440dd86da = 1: e94d57178d tests/docker: Update hexagon cross toolchain to 22.1.0\n 2: b9a5a46b82 = 2: 1fe4b8a0fc target/hexagon: fix incorrect/too-permissive HVX encodings\n 3: 7889db953a = 3: 10fb5b86db target/hexagon/cpu: add HVX IEEE FP extension\n 4: ac72a36fd8 = 4: 8f9a2e2ccf hexagon: group cpu configurations in their own struct\n 5: e24b76d95a = 5: 1bdc772e4a hexagon: print info on \"-d in_asm\" for disabled IEEE FP instructions\n 6: 8c9ded658c = 6: 8923b6c6bc target/hexagon: add v68 HVX IEEE float arithmetic insns\n 7: a89b231b2c = 7: 8e274a7a10 target/hexagon: add v68 HVX IEEE float min/max insns\n 8: 27a5ca1ce3 = 8: 0bd3279ca0 target/hexagon: add v68 HVX IEEE float misc insns\n 9: 7fecae322c = 9: beca620d2e target/hexagon: add v68 HVX IEEE float conversion insns\n10: ebc920dfcf = 10: 96e27588ad target/hexagon: add v68 HVX IEEE float compare insns\n11: d408ee2b2c ! 11: 1a25337356 target/hexagon: add v73 HVX IEEE bfloat16 insns\n @@ target/hexagon/imported/mmvec/ext.idef: ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h\n + \"Vector IEEE max: bf\", VdV.bf[i] = fp_max_bf(VuV.bf[i], VvV.bf[i]);\n + fBFLOAT())\n +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmin_bf, \"Vd32.bf=vmin(Vu32.bf,Vv32.bf)\",\n -+ \"Vector IEEE max: bf\", VdV.bf[i] = fp_min_bf(VuV.bf[i], VvV.bf[i]);\n ++ \"Vector IEEE min: bf\", VdV.bf[i] = fp_min_bf(VuV.bf[i], VvV.bf[i]);\n + fBFLOAT())\n \n /******************************************************************************\n12: cde613d444 = 12: 791f122bfd tests/hexagon: add tests for v68 HVX IEEE float arithmetics\n13: 08abae5ee5 = 13: 7fdbc12ed4 tests/hexagon: add tests for v68 HVX IEEE float min/max\n14: c20a21aad6 = 14: ec6af07a28 tests/hexagon: add tests for v68 HVX IEEE float conversions\n15: 6b473acaf5 = 15: 53e7370709 tests/hexagon: add tests for v68 HVX IEEE float comparisons\n16: 10ebb63b81 ! 16: 392114c4c1 tests/hexagon: add tests for HVX bfloat\n @@ tests/tcg/hexagon/fp_hvx_cmp.c: static void test_cmp_hf(void)\n +\n + /* Common numbers */\n + PREP_TEST();\n -+ TEST_CMP_GT(bf, raw_hf((_Float16)2.2), raw_hf((_Float16)2.1));\n -+ TEST_CMP_GT(bf, raw_hf((_Float16)0), raw_hf((_Float16)-2.2));\n ++ TEST_CMP_GT(bf, BF_two, BF_one);\n ++ TEST_CMP_GT(bf, BF_one, BF_zero);\n + CHECK(bf, 2);\n +\n + /* Infinity vs Infinity/NaN */" }