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{ "id": 2223375, "url": "http://patchwork.ozlabs.org/api/covers/2223375/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260415-ultrarisc-pcie-v3-0-73f06e972616@ultrarisc.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260415-ultrarisc-pcie-v3-0-73f06e972616@ultrarisc.com>", "list_archive_url": null, "date": "2026-04-15T07:21:16", "name": "[v3,0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC", "submitter": { "id": 92886, "url": "http://patchwork.ozlabs.org/api/people/92886/?format=api", "name": "Jia Wang", "email": "wangjia@ultrarisc.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260415-ultrarisc-pcie-v3-0-73f06e972616@ultrarisc.com/mbox/", "series": [ { "id": 499935, "url": "http://patchwork.ozlabs.org/api/series/499935/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499935", "date": "2026-04-15T07:21:17", "name": "riscv: Add PCIe support for UltraRISC DP1000 SoC", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/499935/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2223375/comments/", "headers": { "Return-Path": "\n <linux-pci+bounces-52531-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.a=rsa-sha256 header.s=dkim header.b=IOpGdgYO;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=ultrarisc.com;\n spf=none smtp.mailfrom=ultrarisc.com;\n dkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.b=IOpGdgYO; arc=none smtp.client-ip=218.76.62.146", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=ultrarisc.com; s=dkim; h=Received:From:Subject:Date:Message-Id:\n\tMIME-Version:Content-Type:Content-Transfer-Encoding:To:Cc; bh=8j\n\tgwbAr6xfv3lB+PIrd2FeZsE14YhpxG4VSK+IhOkyo=; b=IOpGdgYOPNf/dgGWV0\n\t+OLkkpREVUYEqnw7kO2Eeo7dvZTGWAYFZSFpYtC3LqWa31/t/bojSNUj+xU8RZEV\n\tPp8c+88mH35hrwBb3G1Y0xt5v0y2hEA4Q0a+rzP3Kg8m+HwVVu0+Z8cWWviQS1dW\n\tqh/1uTDVZ1XeF7/fdT268d0Gg=", "From": "Jia Wang <wangjia@ultrarisc.com>", "Subject": "[PATCH v3 0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC", "Date": "Wed, 15 Apr 2026 15:21:16 +0800", "Message-Id": "<20260415-ultrarisc-pcie-v3-0-73f06e972616@ultrarisc.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "X-B4-Tracking": "v=1; b=H4sIAGw832kC/2XN0Q6CIBgF4FdxXEdDYChd9R6tC8Tf/FupA2U15\n 7sHtmqzy7Od852ZeHAInhyymTgI6LHvYhC7jNjWdBegWMdMOOOKiZzR6TY649BbOlgEKrXUuiy\n UEFqTOBocNPhYwdP5nf1UXcGOSUmNFv3Yu+f6GPLU++Bqi4ecMgoN11JBDUqXx29hb/s7SQeB/\n wjJij+CR4Ibw02uTdFUYkssy/ICIri4OwUBAAA=", "X-Change-ID": "20260310-ultrarisc-pcie-494998763399", "To": "Paul Walmsley <pjw@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>,\n Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alex@ghiti.fr>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Jingoo Han <jingoohan1@gmail.com>,\n Xincheng Zhang <zhangxincheng@ultrarisc.com>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n linux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n Jia Wang <wangjia@ultrarisc.com>", "X-Mailer": "b4 0.15-dev", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776237679; l=3476;\n i=wangjia@ultrarisc.com; s=20260309; h=from:subject:message-id;\n bh=+yU3R6rh+Ql6zbbv0IE0QQGMwTLjaRVc0KqvWKtQBjI=;\n b=gka5ORGZrQQrakysJZjF6f3qoc3FxgtmWrWzKZ+icX3Yt57eP91d/X201RjIzHLabq/Lu+0c6\n bmXfZoTXS6GCF3eRbAizwLTRi9KKRlvhkHYM8JgjMAMAyrp8EQ4Yzxm", "X-Developer-Key": "i=wangjia@ultrarisc.com; a=ed25519;\n pk=XvYkrelqJIIzobY7j+nIg8rsfv5kzaOzuc1UPhd087U=", "X-CM-TRANSID": "AQAAfwAnYUKdPN9poSgCAA--.1324S2", "X-Coremail-Antispam": "1UD129KBjvJXoWxWw1fuw4kKrWUJr1fZF17GFg_yoW5urykpa\n\t98uF4fAF97tr13WF4ft3W8WF1SvF4kArW2qFsFgwnrtF9xuFyUXr9aga1YvF9rArn5Xr12\n\tkr45uw1rGay7ZaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDU0xBIdaVrnRJUUU9l14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n\trVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02\n\t1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j\n\t6F4UM28EF7xvwVC2z280aVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r\n\t4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0\n\tI7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Gr0_Cr1lOx8S6xCaFVCjc4AY6r1j6r\n\t4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628v\n\tn2kIc2xKxwCY1x0262kKe7AKxVW8ZVWrXwCY02Avz4vE-syl42xK82IYc2Ij64vIr41l4I\n\t8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AK\n\txVWUGVWUWwC2zVAF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcV\n\tAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8I\n\tcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r\n\t4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRKE_MDUUUU", "X-CM-SenderInfo": "pzdqwylld63zxwud2x1vfou0bp/1tbiAQAREWncaD0AMgAFsW" }, "content": "This patch series adds PCIe controller support for the UltraRISC DP1000 SoC.\nThe DP1000 is an 8-core 64-bit RISC-V SoC based on UltraRISC CP100 cores,\nsupporting RV64GCBHX ISA with Hardware Virtualization and RISC-V H(v1.0)\nExtension.\n\nThe PCIe controller is based on Synopsys DesignWare PCIe IP.\nThis series adds:\n- Patch 1 adds the basic SoC family Kconfig support for UltraRISC platforms.\n- Patch 2 adds the device tree bindings documentation for the PCIe controller.\n- Patch 3 introduces the PCIe host controller driver.\n\nThe patches have been tested on UltraRISC DP1000 development board with\nvarious PCIe devices including NVMe SSDs and network cards, verifying\nlink establishment, enumeration, and basic data transfer.\n\nSigned-off-by: Jia Wang <wangjia@ultrarisc.com>\n---\nChanges in v3:\n- Fold the MAINTAINERS update into the binding/driver patches and drop\n the standalone MAINTAINERS patch from v2.\n- Patch 1:\n * Trim DP1000-specific ISA/feature details from the help text.\n- Patch 2:\n * Simplify the description formatting and remove the redundant.\n * Drop the max-link-speed property from the binding.\n * Remove the redundant interrupts description line.\n * Clean up the example.\n- Patch 3:\n * Drop unused regmap include.\n * Drop the unused irq_mask[] field.\n * Set pci->max_link_speed = 4 based on the fixed hardware capability.\n- Link to v2: https://patch.msgid.link/20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com\n\nChanges in v2:\n- Rebased onto v7.0-rc7.\n- Patch 1:\n * Removed unnecessary 'depends' line.\n * Fixed help text indentation.\n- Patch 2:\n * No changes.\n- Patch 3:\n * Updated $ref to use 'snps,dw-pcie.yaml' as the base schema.\n * Add interrupts/interrupt-names (MSI + INTx).\n * Drop properties covered by generic DWC/PCI host bindings;\n update example accordingly.\n * Verified the schema passes 'make dt_binding_check' and 'yamllint'.\n- Patch 4:\n * Update commit message.\n * Kconfig: switch PCIE_ULTRARISC to tristate; simplify help text.\n * Convert suspend/resume to dev_pm_ops and called\n `dw_pcie_suspend_noirq()` / `dw_pcie_resume_noirq()`.\n * Use FIELD_MODIFY(); adjust DWC header macros/comments.\n * Added empty `.pme_turn_off()` callback for DP1000 limitation.\n * Renamed link callback to `start_link`.\n * Switched to `module_platform_driver()`.\n * Formatting cleanups (headers order, spacing, variable naming,\n function names)\n- Link to v1: https://patch.msgid.link/20260316-ultrarisc-pcie-v1-0-ef2946ede698@ultrarisc.com\n\n---\nJia Wang (2):\n riscv: add UltraRISC SoC family Kconfig support\n dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller\n\nXincheng Zhang (1):\n PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver\n\n .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 +++++++++++\n MAINTAINERS | 8 +\n arch/riscv/Kconfig.socs | 6 +\n drivers/pci/controller/dwc/Kconfig | 12 ++\n drivers/pci/controller/dwc/Makefile | 1 +\n drivers/pci/controller/dwc/pcie-designware.h | 22 +++\n drivers/pci/controller/dwc/pcie-ultrarisc.c | 186 +++++++++++++++++++++\n 7 files changed, 328 insertions(+)\n---\nbase-commit: bfe62a454542cfad3379f6ef5680b125f41e20f4\nchange-id: 20260310-ultrarisc-pcie-494998763399\n\nBest regards,\n-- \nJia Wang <wangjia@ultrarisc.com>" }