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{ "id": 2220201, "url": "http://patchwork.ozlabs.org/api/covers/2220201/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/cover/20260406-clk-pwm-gpio-v1-0-40d2f3a20aff@radxa.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260406-clk-pwm-gpio-v1-0-40d2f3a20aff@radxa.com>", "list_archive_url": null, "date": "2026-04-06T15:50:00", "name": "[0/2] pwm: clk-pwm: Add GPIO support for constant output levels", "submitter": { "id": 90715, "url": "http://patchwork.ozlabs.org/api/people/90715/?format=api", "name": "Xilin Wu", "email": "sophon@radxa.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/cover/20260406-clk-pwm-gpio-v1-0-40d2f3a20aff@radxa.com/mbox/", "series": [ { "id": 498878, "url": "http://patchwork.ozlabs.org/api/series/498878/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=498878", "date": "2026-04-06T15:50:00", "name": "pwm: clk-pwm: Add GPIO support for constant output levels", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498878/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2220201/comments/", "headers": { "Return-Path": "\n <linux-pwm+bounces-8495-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8495-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=18.132.163.193", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=radxa.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=radxa.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqDMM1SvKz1yFt\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 07 Apr 2026 01:51:11 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id BC3013013262\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 6 Apr 2026 15:51:07 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 4A69F2D594F;\n\tMon, 6 Apr 2026 15:51:06 +0000 (UTC)", "from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 09BD426CE2D;\n\tMon, 6 Apr 2026 15:51:01 +0000 (UTC)", "from [192.168.30.32] ( [116.234.14.100])\n\tby bizesmtp.qq.com (ESMTP) with\n\tid ; Mon, 06 Apr 2026 23:50:05 +0800 (CST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775490666; cv=none;\n b=ktnRtE4bT3TiNjUYh/KO9q3R4URFdKplM+9HWAIIroJ6hrFQZxGF0x1OoKJHe4lG2IPYOTahmUcB+UPHoOWvGxFW2VMJ+O+CvNgBHkuX6d62A89pBZtvr3ycuEha9vv4Zjc/7IHAnNMAwaOu/VY+OMsTLziMAKYicAE4UuMhylg=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775490666; c=relaxed/simple;\n\tbh=UA1pIDqZTcN0wblz4FqWp/DqMz+poNs9kVactYjBrxo=;\n\th=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc;\n b=rNwWUzdWLWrfEh1DZLLfZBC4NruXrPxXVSJ5ox1lSA1aToLtns/9HzZwjgYoy3y2tqv0Kb4BUHsGOwoumi1YQwdcpmeg+pJmkWQmXQm4WmhGQipZDmUPo3weLWUkBbdm82eP3N4o45spZWg8ctQsg5ntuYw98pI5WUSqu3526IM=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=radxa.com;\n spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=18.132.163.193", "X-QQ-mid": "zesmtpsz5t1775490607t015ef3cd", "X-QQ-Originating-IP": "6hbAr8UySjcB8zecLV1wQa7GbFzaP8lEedladUubDsI=", "X-QQ-SSF": "0000000000000000000000000000000", "X-QQ-GoodBg": "0", "X-BIZMAIL-ID": "9436570935921105278", "EX-QQ-RecipientCnt": "10", "From": "Xilin Wu <sophon@radxa.com>", "Subject": "[PATCH 0/2] pwm: clk-pwm: Add GPIO support for constant output\n levels", "Date": "Mon, 06 Apr 2026 23:50:00 +0800", "Message-Id": "<20260406-clk-pwm-gpio-v1-0-40d2f3a20aff@radxa.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "X-B4-Tracking": "v=1; b=H4sIAAAAAAAC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE\n vPSU3UzU4B8JSMDIzMDEwMz3eScbN2C8lzd9ILMfF3zNDPjJGMLSwOLRFMloJaCotS0zAqwcdG\n xEH5xaVJWanIJyAyl2loAFH4y/nAAAAA=", "X-Change-ID": "20260406-clk-pwm-gpio-7f63b38908a5", "To": "=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Nikita Travkin <nikita@trvn.ru>", "Cc": "linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n Xilin Wu <sophon@radxa.com>", "X-Mailer": "b4 0.15.1", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=1293; i=sophon@radxa.com;\n h=from:subject:message-id; bh=UA1pIDqZTcN0wblz4FqWp/DqMz+poNs9kVactYjBrxo=;\n b=owGbwMvMwCVmdFg0fe08Iz/G02pJDJmXr+n+OtZd4r/p2/L8D1raZxbr3ghIMH3m2u10rNJYs\n 5J/e+nsjlIWBjEuBlkxRRaFeIa57JW5156KlerBzGFlAhnCwMUpABNxsWL47yRtoz/ndvOLORlG\n 2YW21hvnvJAQd1RVO6bKajhn+VV5W4b/pbd2xed5OFmfSbDyWBMj4nfrf8KkqvgqUe5tnf0MXVd\n ZAA==", "X-Developer-Key": "i=sophon@radxa.com; a=openpgp;\n fpr=205F009D07796DD6E516752E32C31567AD9E324E", "X-QQ-SENDSIZE": "520", "Feedback-ID": "zesmtpsz:radxa.com:qybglogicsvrsz:qybglogicsvrsz3b-0", "X-QQ-XMAILINFO": "OHFB8ysKYMMnNYH5jddxhIytVYIU95tLqO7r6r0BENkgD4GHYt2aLQRE\n\tyW6V1R52xmdCE3OxJdk6OLe7LdZs3HCX+EFHcaAdDHifNmaSvKw+QJTHIk+0104P3/7MEJA\n\tpNvZgHx1+f8x29fChg0gduxZtF1QWW95Yy700JCf6IiFca8uRKdcASy6ooB3G76Kz76aAFJ\n\trd56GKqj+SNWN87OgWMf3G2HxDJz0jtRL0Un0B8AvmLbfYeD17CkU+fIdjkblHjIJ3B0gx9\n\tVcz7skx6mtpxdvKNVdJdTg4LP5PSlcETk9NcbHIAzRt6SbZ1Cqz/+qzDle3R2OyUhDhoL+0\n\tbtaWr75QPpzZ59kiBam+jHZ5PTyrqFjtccgq1H43t8hBk58w4e6i0GaGs3iK9h7Q3v0tNyG\n\tf/x83KyHSa3OV0VkaUbdRs8nQjSjpV12pikYB1NapT9XbsFGuPWr7oXwyjHHt/XnUexG8v6\n\tM5js/Q4T7NJTvyxBjaKeg0RwU6jTUFGtTh4jJ+6yJDaF5KblgdRtzMrWu6aQOCgD0kphgvU\n\t9HkPN5Yot8nJWYY/x6aW//R8LX/9Rrrw3D56WKvlJmEQc8ijmNlm2OMoJ6kF4R/E4WJf38O\n\t8tmVJ90Q/8931MC8MsoEd5K3oYeYrClpWiHKe0HlV9uMe8snYwfWrpCqulI27HeYPmKxxBp\n\tMZxho9dozxo/b9wELRzf8KTrDlgxsFV0APzjexc3/+j7nVbo2bNu1b8GB6eoCEeMI/Blcim\n\tOvxVM/dLq7RCzvveAMqb2TkRiuIh//H930a2MorU6BYWJZYqAqiXbQNqGxmJLHhZJYnJSuh\n\tX4uUu58r7+eLOSkJOr37k6j5/7agOOj37RJfesK9NUQHMXFZq/T6uq7K5rC9Hbj3WtdF1m5\n\tzN457efkR10lVZyYUjjq33wFAr0+rwKXER5qRwOFKYSPZLWgak9qMCO+X1FBJg2tTQEnUJJ\n\tJJcKMtkdWad9fQguiP9x5ZoETKXaaY1u+svGBcaQUXc/dLQJfx9uT3zEvh0g1RjzeBn/zMf\n\tD12XJDSCD/Y5pGqh5l71+Ey0qgAKNz8Rn9w5nBfxyUJj6/BgqVpTwA9Vmpsvl+4c7AFWMvE\n\tRX8PfuMDI7w", "X-QQ-XMRINFO": "NyFYKkN4Ny6FuXrnB5Ye7Aabb3ujjtK+gg==", "X-QQ-RECHKSPAM": "0" }, "content": "The clk-pwm driver uses a clock with duty cycle control to generate\nPWM output. However, when the PWM is disabled or a 0%/100% duty cycle\nis requested, the clock must be stopped, and the resulting pin level\nis undefined and hardware-dependent.\n\nThis series adds optional GPIO and pinctrl support to the clk-pwm\ndriver. When a GPIO and pinctrl states (\"default\" for clock mux,\n\"gpio\" for GPIO mode) are provided in the device tree, the driver\nswitches the pin to GPIO mode and drives a deterministic output level\nfor disabled/0%/100% states. For normal PWM output the pin is switched\nback to its clock function mux. If no GPIO is provided, the driver\nfalls back to the original clock-only behavior.\n\nSigned-off-by: Xilin Wu <sophon@radxa.com>\n---\nXilin Wu (2):\n dt-bindings: pwm: clk-pwm: add optional GPIO and pinctrl properties\n pwm: clk-pwm: add GPIO and pinctrl support for constant output levels\n\n Documentation/devicetree/bindings/pwm/clk-pwm.yaml | 36 ++++++++++-\n drivers/pwm/pwm-clk.c | 72 ++++++++++++++++++++--\n 2 files changed, 101 insertions(+), 7 deletions(-)\n---\nbase-commit: 2febe6e6ee6e34c7754eff3c4d81aa7b0dcb7979\nchange-id: 20260406-clk-pwm-gpio-7f63b38908a5\n\nBest regards,\n-- \nXilin Wu <sophon@radxa.com>" }