Cover Letter Detail
Show a cover letter.
GET /api/covers/2220170/?format=api
{ "id": 2220170, "url": "http://patchwork.ozlabs.org/api/covers/2220170/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260406150434.407201-1-pierrick.bouvier@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260406150434.407201-1-pierrick.bouvier@linaro.org>", "list_archive_url": null, "date": "2026-04-06T15:04:20", "name": "[v7,00/14] target/arm: single-binary", "submitter": { "id": 85798, "url": "http://patchwork.ozlabs.org/api/people/85798/?format=api", "name": "Pierrick Bouvier", "email": "pierrick.bouvier@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260406150434.407201-1-pierrick.bouvier@linaro.org/mbox/", "series": [ { "id": 498869, "url": "http://patchwork.ozlabs.org/api/series/498869/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498869", "date": "2026-04-06T15:04:20", "name": "target/arm: single-binary", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/498869/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2220170/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=qFhypsFr;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqCMT5RTwz1yGn\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 07 Apr 2026 01:06:12 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w9lVS-0002sZ-2z; Mon, 06 Apr 2026 11:04:50 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <pierrick.bouvier@linaro.org>)\n id 1w9lVP-0002rv-SQ\n for qemu-devel@nongnu.org; Mon, 06 Apr 2026 11:04:48 -0400", "from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <pierrick.bouvier@linaro.org>)\n id 1w9lVN-0003q9-AP\n for qemu-devel@nongnu.org; Mon, 06 Apr 2026 11:04:47 -0400", "by mail-pl1-x630.google.com with SMTP id\n d9443c01a7336-2aaf59c4f7cso18037105ad.1\n for <qemu-devel@nongnu.org>; Mon, 06 Apr 2026 08:04:44 -0700 (PDT)", "from pc.taild8403c.ts.net (216-71-219-44.dyn.novuscom.net.\n [216.71.219.44]) by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b274979d72sm137770075ad.51.2026.04.06.08.04.42\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 06 Apr 2026 08:04:42 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1775487883; x=1776092683; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:from:to:cc:subject:date:message-id:reply-to;\n bh=xhWX4LN6/7U+l0GQfGNZYyz9ZAXayPixhHRwsoCZtho=;\n b=qFhypsFrXCREBjfjAdLxtpvu8oLFpSKLvcgHz1RfMYihbWzO2zLpk0Xuryx+Z8VwPY\n sh1fV4EQ+mG8RQ/RAMNhGJQDXkuHvwCU3KH5dSjYwWy8Q/R52G536QDVzpWAnzP2UE7m\n cyr16BFhXuGhFL4AZBwPivo08zzvFDxRwSmWZyNRQ39F1fNUMPGxvz9BflpZh4Qn9+Om\n atNbblG8Yi9Xw2gHTJSJPmt4F67Wv6SCfiUNy517mihFHPVMncVibmU4m/ivxjEYnOCQ\n 2NmlpeXQQJe2FpTtjmhXs17gENqPihDCWEkmxZgtxxBWUKIMv8XwVINVXCJ24eCLg70R\n EgOQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775487883; x=1776092683;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date\n :message-id:reply-to;\n bh=xhWX4LN6/7U+l0GQfGNZYyz9ZAXayPixhHRwsoCZtho=;\n b=TZpkqwqQ+F+UU63Mc5LbfQpBe4lT4gmMWYucXxLweKKC36VtQvw7wJhR4FgMtltBAm\n d6+dzzCXFj3P5glpgu2AL/weAwssOf6IJX5bo3SD93h2wr1DXdhW4lVGV0zesAYb/r1/\n EWMwbq1QI3/aVj3KpV4DL7blrAQxOfkHgmdaulsMCKb5WKG7qNQpzRdeoaS+u2gw7+SB\n oB0hNpihk5mUlFmCx727PeiyPGWBFqvuvDEJWXilTMiJBZsGjo+e42B1POK6XF2dSMqp\n wfeCBBjFiRBdUb9jA3ZZlDbeqzYzz2/s553sAnZ/Q8ivB+l11XCtL4896+hcM88TMzsj\n xs6A==", "X-Gm-Message-State": "AOJu0Yz5EvASEe9XnrtnmgZlsDA5WpGWaAQZcVxcw3vmh8h2ssh4HBbH\n HvIKvlyy0p9i7mryOvrBJXx1iTeJbZjCZYbBFjsV1+oRC0JlK4Tt5CbdATKOg6V8w0PnpVQJJFP\n mKbJyooaqZg==", "X-Gm-Gg": "AeBDieufySBanpwx4v9dfja+c6wxNPv3P6ojAvBQwb5MNqIM348AqS6me/WeWOj6LeJ\n BVE6VoirjQUIkUhdb2txydwUE+UBuEJ3abR7DO1VGljzpuZAp9XUGkvBHnjicC8fUoNuYmlQca4\n zstTYxrHRdkjjkef0zdg37mdLL6UM5iQ6x8MdNQucFY9xn6W4Aol/Q2nuj/jp1U0lj55iMjWyNz\n JkgAY61yTrHS6UUgX2YdprJKsZ2eTmw1BV6mrkDWBXp112Pk2S1yJnKvqrxwuE5SC65jDxqm4z5\n sXo82xHc5B75hzaXvhsyy4cweOiMkCp5s+N/shDAAtG2/DIffXAOy/ErtiqBcz3x/slZZM2NEIv\n 8lltGYKVcHpNl0vm0DPZ3y7uyxJkqMRnLpk8jVyrmwaLOyDNuQ1ipgReSxyGo/LQFY/nF+lr0PD\n /fDQp66R4UH+0iovh3VogAaAsVQoZGOvbC286m8T35zXTsuy60aE7PK3vKQMOB+MNqWoKQpeMTY\n q7ZOzNoax/Gvzo=", "X-Received": "by 2002:a17:903:3804:b0:2b0:59c4:e9dc with SMTP id\n d9443c01a7336-2b28170f376mr139020735ad.22.1775487883264;\n Mon, 06 Apr 2026 08:04:43 -0700 (PDT)", "From": "Pierrick Bouvier <pierrick.bouvier@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-arm@nongnu.org, Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>, philmd@linaro.org,\n jim.macarthur@linaro.org, Paolo Bonzini <pbonzini@redhat.com>,\n Richard Henderson <richard.henderson@linaro.org>", "Subject": "[PATCH v7 00/14] target/arm: single-binary", "Date": "Mon, 6 Apr 2026 08:04:20 -0700", "Message-ID": "<20260406150434.407201-1-pierrick.bouvier@linaro.org>", "X-Mailer": "git-send-email 2.47.3", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::630;\n envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x630.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This series tackles (most of) the rest of target/arm, especially tcg folder.\n\nWe extract tcg memory operation in a new header, with a new type representing\nvirtual addresses.\n\nInitially, I went down the way to have a dynamic definition of TCGv, which\nrequired much more boilerplate and runtime checks. After discussing with\nRichard, I realized it was not needed, and that could simply split 32 and 64 bit\nproperly in different files instead. This approach will not work with other\narchitectures, requiring something else, but it's enough for target/arm.\n\nFiles left are:\n- target/arm/tcg/mve_helper.c\n- target/arm/tcg/m_helper.c\n- target/arm/tcg/cpu32.c\n\nv7\n--\n\n- add parameter to translator_loop to indicate address type for current tb.\n- remove TCGv from target/arm/tcg/translate.c\n\nv6\n--\n\n- meson.build: extract decode files in separate variables and explicitly include\n them in user and system code. The duplication is now minimized: one instance\n for all system binaries, and one per user binary.\n\nv5\n--\n\n- reimplemented what v0 did with new approach defining new tcg-op-mem header\n- reapply all straightforward patches from v0\n- only translate.c is left, but first want to validate that changes here are ok\n for maintainers before doing more.\n\nv0\n--\n\nSee original thread:\nhttps://lore.kernel.org/qemu-devel/20260109053158.2800705-1-pierrick.bouvier@linaro.org/#t\n\nNote about v1 -> v4\n-------------------\n\n- After v0 which was trying to do too many changes, v1 to v4 focused on smaller\n things, and all patches have been merged already.\n https://patchew.org/QEMU/20260219040150.2098396-1-pierrick.bouvier@linaro.org/\n\nPierrick Bouvier (14):\n include/tcg/tcg-op: extract memory operations to tcg-op-mem.h\n target/arm/translate.h: remove tcg-op.h include\n target/arm/tcg/translate.h: remove tcg-op-gvec.h include\n target/arm/tcg/translate.h: remove TARGET_AARCH64\n target/arm/tcg/translate-vfp.c: make compilation unit common\n target/arm/tcg/translate-neon.c: make compilation unit common\n target/arm/tcg/translate-mve.c: make compilation unit common\n target/arm/tcg/translate-m-nocp.c: make compilation unit common\n target/arm/tcg/op_helper.c: make compilation unit common\n target/arm/tcg/gengvec.c: make compilation unit common\n target/arm/tcg/translate.c: remove MO_TE usage\n target/arm/tcg/translate.c: replace target_ulong with uint32_t\n tcg/translator: add parameter to translator_loop for current addr type\n target/arm/tcg/translate.c: replace TCGv with TCGv_va\n\n include/exec/translator.h | 4 +-\n include/tcg/tcg-op-mem.h | 126 +++++++++++++++++++++++++++++++\n include/tcg/tcg-op.h | 100 +-----------------------\n include/tcg/tcg.h | 5 ++\n target/arm/tcg/translate.h | 14 +---\n accel/tcg/translator.c | 4 +-\n target/alpha/translate.c | 3 +-\n target/arm/tcg/op_helper.c | 1 -\n target/arm/tcg/stubs32.c | 17 +++++\n target/arm/tcg/translate-a64.c | 1 +\n target/arm/tcg/translate-sme.c | 1 +\n target/arm/tcg/translate-sve.c | 1 +\n target/arm/tcg/translate.c | 36 ++++-----\n target/avr/translate.c | 3 +-\n target/hexagon/translate.c | 3 +-\n target/hppa/translate.c | 3 +-\n target/i386/tcg/translate.c | 3 +-\n target/loongarch/tcg/translate.c | 3 +-\n target/m68k/translate.c | 3 +-\n target/microblaze/translate.c | 3 +-\n target/mips/tcg/translate.c | 3 +-\n target/or1k/translate.c | 3 +-\n target/ppc/translate.c | 3 +-\n target/riscv/translate.c | 3 +-\n target/rx/translate.c | 3 +-\n target/s390x/tcg/translate.c | 3 +-\n target/sh4/translate.c | 3 +-\n target/sparc/translate.c | 3 +-\n target/tricore/translate.c | 3 +-\n target/xtensa/translate.c | 3 +-\n target/arm/tcg/meson.build | 51 +++++++++----\n 31 files changed, 255 insertions(+), 160 deletions(-)\n create mode 100644 include/tcg/tcg-op-mem.h\n create mode 100644 target/arm/tcg/stubs32.c" }