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{ "id": 2219989, "url": "http://patchwork.ozlabs.org/api/covers/2219989/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260405154154.46829-1-me@ziyao.cc/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260405154154.46829-1-me@ziyao.cc>", "list_archive_url": null, "date": "2026-04-05T15:41:52", "name": "[v3,0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports", "submitter": { "id": 92226, "url": "http://patchwork.ozlabs.org/api/people/92226/?format=api", "name": "Yao Zi", "email": "me@ziyao.cc" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260405154154.46829-1-me@ziyao.cc/mbox/", "series": [ { "id": 498791, "url": "http://patchwork.ozlabs.org/api/series/498791/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498791", "date": "2026-04-05T15:41:52", "name": "PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498791/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2219989/comments/", "headers": { "Return-Path": "\n <linux-pci+bounces-51920-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ziyao.cc header.i=me@ziyao.cc header.a=rsa-sha256\n header.s=zmail header.b=Tfnf3itI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775403766; c=relaxed/simple;\n\tbh=ocON1VQDAffjSTN+FN6PCUJPWpGqHythNb1L45yxuKk=;\n\th=From:To:Cc:Subject:Date:Message-ID:MIME-Version;\n b=l9CMZ/FJW/4SOR4vf4TSuPfY0KX+B6fgQRFEmnxloMmIl23Odviw/Mroc4XJ361CY2/3rArun3X1LN9KCrXME0BO2BqnfZRKwcLyr+PDJk+uuaM65Y5gjXoHbhGlcTGngcBRYVR9KoZKHR5dJ6B5Q3rEOcAgSe2uX49rCv/qT/g=", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com;\n s=zohoarc;\n\tt=1775403742;\n h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:MIME-Version:Message-ID:Subject:Subject:To:To:Message-Id:Reply-To;\n\tbh=24hyvMXW0XjpNbHAgW3h4Frtz4FpSP6l+QFo6AkVhNk=;\n\tb=TfCzjcc3r5QgnBlM/I2/3JpmCNBPPzLxvDA1lQWrZsVzLwkMdggDwkro937Tko/POyeOXEB/PT27tUkXMhGFiPfQT276Nb1ai4KQreJE/ZNGdC1zAUOBO8LKRCVPwDuj65CmE+4UAvaKTvNThr2Ztl7hyXsT5xHdbF3H/v8Feq4=" ], "ARC-Authentication-Results": [ "i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=quarantine dis=none) header.from=ziyao.cc;\n spf=pass smtp.mailfrom=ziyao.cc;\n dkim=pass (1024-bit key) header.d=ziyao.cc header.i=me@ziyao.cc\n header.b=Tfnf3itI; arc=pass smtp.client-ip=136.143.188.15", "i=1; mx.zohomail.com;\n\tdkim=pass header.i=ziyao.cc;\n\tspf=pass smtp.mailfrom=me@ziyao.cc;\n\tdmarc=pass header.from=<me@ziyao.cc>" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1775403742;\n\ts=zmail; d=ziyao.cc; i=me@ziyao.cc;\n\th=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To;\n\tbh=24hyvMXW0XjpNbHAgW3h4Frtz4FpSP6l+QFo6AkVhNk=;\n\tb=Tfnf3itIpo4p0ml7SKsXdn25GKavEnONi7lnCHgXBTZIziobb5mFq82OhJtgDpiP\n\tNvUVyC0mAeBX9iga/VsSRPVOcWvd+M8eC4HdHrHCJH1xOw2WcyllgbUTc9aBTdzoYUF\n\tXnSPT0IrtNPuy9nnVEgsEhZf4I4peoibzHE/6y7c=", "From": "Yao Zi <me@ziyao.cc>", "To": "Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Siddharth Vadapalli <s-vadapalli@ti.com>, Hans Zhang <18255117159@163.com>,\n Kishon Vijay Abraham I <kishon@kernel.org>,\n Chen Wang <unicorn_wang@outlook.com>,\n Manikandan K Pillai <mpillai@cadence.com>,\n Christophe JAILLET <christophe.jaillet@wanadoo.fr>,\n Inochi Amaoto <inochiama@gmail.com>, Han Gao <rabenda.cn@gmail.com>", "Cc": "linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tYao Zi <me@ziyao.cc>", "Subject": "[PATCH v3 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root\n Ports", "Date": "Sun, 5 Apr 2026 15:41:52 +0000", "Message-ID": "<20260405154154.46829-1-me@ziyao.cc>", "X-Mailer": "git-send-email 2.53.0", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-ZohoMailClient": "External" }, "content": "After talking to Inochi privately, I'll take the patch instead.\n\nThis series defines quirk flags for Cadence PCIe host driver to allow\ndisabling advertisement of ASPM L0s/L1 states by overriding LNKCAP\nregister, and set them in SG2042 PCIe driver since SG2042's\nimplementation is broken.\n\nI've considered to re-write LNKCAP after cdns_pcie_host_setup() in\nSG2042 platform glue, like what has been done in the v1 of patch.\nHowever, cdns_pcie_host_setup() performs pci_host_probe(), which finally\ninvokes set_pcie_port_type() on the root port. It reads ASPM-related\nLNKCAP, which might lead to dangling pci_dev.aspm_{l0s,l1}_support\nvalues. Early PCI device fixup won't work for similar reasons, since the\nfixup is performed in pci_setup_device() after calling\nset_pcie_port_type().\n\nIt's hard to fix up the LNKCAP earlier than invokation of\ncdns_pcie_host_setup() in SG2042's platform glue, either, since\nthe function also performs resource allocation/mapping, and we have no\naccess to the RC registers before it returns.\n\nThe safest solution which also depends on no PCI subsystem\nimplementation detail is to have the LNKCAP fixed up right before\ninforming the PCI subsystem of the device through pci_host_probe(), so\nhere come the quirk flags and the ASPM advertisement disabling logic\nin the core Cadence PCIe driver.\n\nThis series is based on next-20260403, thanks for your time and review.\n\nChanged from v2:\n- Use flags to allow platform glues to inform the core driver that\n ASPM implementation is broken and should be disabled, instead of\n introducing platform-specific hooks to do so.\n- Fix Co-developed-by tag in patch 2\n- Link to v2: https://lore.kernel.org/linux-pci/20260227181925.52475-1-me@ziyao.cc/\n\nChanged from v1:\n- Disable L0s/L1 capabilities through LNKCAP instead of LNKCTL\n- Introduce platform-specific init/deinit hooks (new PATCH 1) to\n realiably overwrite PCIe RC properties\n- Link to v1: https://lore.kernel.org/all/20260109040756.731169-2-inochiama@gmail.com/\n\nChanged from the original patch:\n- Use driver to mask the ASPM advertisement\n- Separate from the following patch\n https://lore.kernel.org/all/20251225100530.1301625-1-inochiama@gmail.com\n\nYao Zi (2):\n PCI: cadence: Add flags for disabling ASPM support advertisement\n PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports\n\n .../controller/cadence/pcie-cadence-host.c | 7 +++++++\n drivers/pci/controller/cadence/pcie-cadence.h | 19 +++++++++++++++++++\n drivers/pci/controller/cadence/pcie-sg2042.c | 2 ++\n 3 files changed, 28 insertions(+)" }