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{ "id": 2219049, "url": "http://patchwork.ozlabs.org/api/covers/2219049/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1775122853.git.matheus.bernardino@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-02T10:47:17", "name": "[v2,00/16] hexagon: add missing HVX float instructions", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1775122853.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 498468, "url": "http://patchwork.ozlabs.org/api/series/498468/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498468", "date": "2026-04-02T10:47:20", "name": "hexagon: add missing HVX float instructions", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498468/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2219049/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=N5ev4dLx;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com 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Du84j8YxZw", "X-Received": [ "by 2002:a05:7300:fb8b:b0:2c1:59ea:10f7 with SMTP id\n 5a478bee46e88-2c9327a3825mr3596702eec.18.1775126856242;\n Thu, 02 Apr 2026 03:47:36 -0700 (PDT)", "by 2002:a05:7300:fb8b:b0:2c1:59ea:10f7 with SMTP id\n 5a478bee46e88-2c9327a3825mr3596685eec.18.1775126855690;\n Thu, 02 Apr 2026 03:47:35 -0700 (PDT)" ], "From": "Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>", "To": "qemu-devel@nongnu.org", "Cc": "richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v2 00/16] hexagon: add missing HVX float instructions", "Date": "Thu, 2 Apr 2026 03:47:17 -0700", "Message-Id": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.37.2", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Authority-Analysis": "v=2.4 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RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This patchset adds 59 HVX floating point instructions from Hexagon\nrevisions v68 and v73 that were missing in qemu. Tests are also added at\nthe end.\n\nv1: https://lore.kernel.org/qemu-devel/cover.1774271525.git.matheus.bernardino@oss.qualcomm.com/\n\nChanges in v2:\n\n - Renamed kvx_ieee.{c,h} to hvx_ieee_fp.{c,h}\n - Dedicated HVX floating-point status: Added a separate hvx_fp_status\n field in CPUArchState for HVX IEEE FP operations. This isolates HVX\n FP state from scalar FP operations and allows configuring the\n correct default NaN pattern for HVX (0x7FFF... instead of\n 0xFFFF...)\n - Disabled IEEE FP behavior: When the HVX IEEE FP extension is\n disabled, instructions now zero out their destination registers\n instead of being complete no-ops. This matches actual hardware\n behavior more closely\n - Fixed NaN comparison ordering: Rewrote the comparison functions\n (fCMPGT_SF, fCMPGT_HF, fCMPGT_BF) with proper NaN ordering\n semantics: QNaN > SNaN > +Inf > numbers > -Inf > SNaN_neg >\n QNaN_neg\n - Simplified FP helper macros: Removed redundant NaN checks from\n DEF_FP_INSN_2/DEF_FP_INSN_3 macros since the softfloat library\n handles NaN propagation correctly when default_nan_mode is enabled\n - Expanded test coverage:\n - Tests to cover NaN vs NaN, NaN vs Inf, and NaN vs regular numbers\n - Added tests for vcmp_gtand/vcmp_gtor variants\n - Added bfloat tests\n - Added .new register usage tests for disabled IEEE FP\n\nBrian Cain (1):\n tests/docker: Update hexagon cross toolchain to 22.1.0\n\nMatheus Tavares Bernardino (15):\n target/hexagon: fix incorrect/too-permissive HVX encodings\n target/hexagon/cpu: add HVX IEEE FP extension\n hexagon: group cpu configurations in their own struct\n hexagon: print info on \"-d in_asm\" for disabled IEEE FP instructions\n target/hexagon: add v68 HVX IEEE float arithmetic insns\n target/hexagon: add v68 HVX IEEE float min/max insns\n target/hexagon: add v68 HVX IEEE float misc insns\n target/hexagon: add v68 HVX IEEE float conversion insns\n target/hexagon: add v68 HVX IEEE float compare insns\n target/hexagon: add v73 HVX IEEE bfloat16 insns\n tests/hexagon: add tests for v68 HVX IEEE float arithmetics\n tests/hexagon: add tests for v68 HVX IEEE float min/max\n tests/hexagon: add tests for v68 HVX IEEE float conversions\n tests/hexagon: add tests for v68 HVX IEEE float comparisons\n tests/hexagon: add tests for HVX bfloat\n\n target/hexagon/cpu.h | 10 +-\n target/hexagon/cpu_bits.h | 10 +-\n target/hexagon/mmvec/hvx_ieee_fp.h | 128 ++++++\n target/hexagon/mmvec/macros.h | 8 +\n target/hexagon/mmvec/mmvec.h | 3 +\n target/hexagon/printinsn.h | 2 +-\n target/hexagon/translate.h | 1 +\n tests/tcg/hexagon/hex_test.h | 32 ++\n tests/tcg/hexagon/hvx_misc.h | 73 ++++\n target/hexagon/attribs_def.h.inc | 9 +\n disas/hexagon.c | 3 +-\n target/hexagon/arch.c | 8 +\n target/hexagon/cpu.c | 18 +-\n target/hexagon/decode.c | 4 +-\n target/hexagon/mmvec/hvx_ieee_fp.c | 275 +++++++++++++\n target/hexagon/printinsn.c | 7 +-\n target/hexagon/translate.c | 5 +-\n tests/tcg/hexagon/fp_hvx.c | 226 +++++++++++\n tests/tcg/hexagon/fp_hvx_cmp.c | 279 ++++++++++++++\n tests/tcg/hexagon/fp_hvx_cvt.c | 219 +++++++++++\n tests/tcg/hexagon/fp_hvx_disabled.c | 57 +++\n target/hexagon/gen_tcg_funcs.py | 11 +\n target/hexagon/hex_common.py | 37 ++\n target/hexagon/imported/mmvec/encode_ext.def | 126 ++++--\n target/hexagon/imported/mmvec/ext.idef | 363 +++++++++++++++++-\n target/hexagon/meson.build | 1 +\n .../dockerfiles/debian-hexagon-cross.docker | 10 +-\n tests/tcg/hexagon/Makefile.target | 14 +\n 28 files changed, 1891 insertions(+), 48 deletions(-)\n create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.h\n create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.c\n create mode 100644 tests/tcg/hexagon/fp_hvx.c\n create mode 100644 tests/tcg/hexagon/fp_hvx_cmp.c\n create mode 100644 tests/tcg/hexagon/fp_hvx_cvt.c\n create mode 100644 tests/tcg/hexagon/fp_hvx_disabled.c" }