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{ "id": 2218324, "url": "http://patchwork.ozlabs.org/api/covers/2218324/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260401010231.4166776-1-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401010231.4166776-1-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-01T01:02:20", "name": "[00/11] hw/arm/smmuv3-accel: Resolve AUTO properties", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260401010231.4166776-1-nathanc@nvidia.com/mbox/", "series": [ { "id": 498265, "url": "http://patchwork.ozlabs.org/api/series/498265/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498265", "date": "2026-04-01T01:02:20", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498265/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2218324/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=ewUWGR7E;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=YBzZ2Eo6p1Dl0vN5H0RBSs0vCydnH4L9+TGgAvbIJIE=;\n b=kwFbirfZHkg1X6kLHBurmCVV11qPKSO6v+3UvCGdbNQUs2kjPULcpl/1TetzqksQm68wQ9QODJ+2GIOJZXFoGTmyn3mc2ten1v8+t9/HGehJIP6Ao7hCXTut07pPxCqi5OGLQKYRd+KGI2fKc8FVdYBjLKbTRQOqae6rw7Z5dXb8t8ZQg9DO+QZ77UEfFS344M6ldocmVM4H/k+wC9CxUNyhatE1gDcZlYxfTHE7NPGISWD7p7u5HO7+vowGhtVX0BGiMoza+ygflF2D/Y/9zU93DT/palJy4mU5alVRTc7qcXElZOqeIwdF37rF596mvbKHS8jFz4b9HLdA9UVY+g==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=YBzZ2Eo6p1Dl0vN5H0RBSs0vCydnH4L9+TGgAvbIJIE=;\n b=ewUWGR7EWCkaeo2tFil7giY8upuwOeqp65xb2I7CrHEyhe0ESuuQhooDHAzYukIsWl6dd19Ecb36bPQC9u5sfgLB+9c4/fEFatcnCCdUL/J7ZIKYBtzZf8b2Q511k7gakX/PcpMMaUZqtM4T4rYmHvHF2lNuficCXlL1JtFsILefUng2IMs78S+ClOcB3l5mhv7CRJ2DPKFKrNiBGUblV+kPHCfLlUlQy48EMlYrc4yuJtxWivbS/2Zdk0cQF/vTkwwCedzN+0sg3aTdHBnu95x4sJ99J+lEwhAqgyaKS06/HW4065Jglj5KFGIkjsdUZ+bDipoRztJaPuuJf0NpQw==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Yi Liu <yi.l.liu@intel.com>, Eric Auger <eric.auger@redhat.com>,\n Zhenzhong Duan <zhenzhong.duan@intel.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Alex Williamson <alex@shazbot.org>,\n =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH 00/11] hw/arm/smmuv3-accel: Resolve AUTO properties", "Date": "Tue, 31 Mar 2026 18:02:20 -0700", "Message-ID": "<20260401010231.4166776-1-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ0PR13CA0184.namprd13.prod.outlook.com\n (2603:10b6:a03:2c3::9) To DS2PR12MB9567.namprd12.prod.outlook.com\n (2603:10b6:8:27c::8)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PR12MB9567:EE_|CH1PR12MB9647:EE_", "X-MS-Office365-Filtering-Correlation-Id": "1011bd58-4a0a-4fe5-81f7-08de8f8a5bbb", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|7416014|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n +uU1uCwnlHwXSQjRmzdoj4FmMUy5EonjB1zv/eC/duYcF27JjZAgOxfUjzp4XroNKI95zpaZEQyhNExCLyKygk4CEFwKPmoHTIqbaK5QK8uqURkTqo1LMeeA2xIychEQtY7F285Ndecz89A37SFJi3NwKixtF+paPAhcJ2PR5hbkCDB9cCHgRarKnwdPW4jlTH3XP8pVVL0MDeKd84AqdPgqCpZpGwATxKWfsswHmtAqppf+90w6lM+Q2LgBDqiNza2ln2xGuo7mF6+60TzTR3tgV7AdscwCury/ifl4Uk6ReBboYlmF536vdQ479+JhTt1MVdOAFuQjhXJrR85Uq5K55IvejNqWq7jORulLkOLiDK0NArKgZAUfYCAsIjUyxaAJyWMBuI+UjCsqVtNxTkY242Jyo9gpKyXm/VLhZ7VTKrpPSeYJg/EZMsN/ywMTiIp8Kiz/Pwog4NNpxRXL382G5cmjClJ+Lm//xxdXgqkNxFw7d+dDVB5HFP3PgzJXLlAwoA37THX+AhR43tezX36S6ekwOMqLaSy1BSQxJOVUFEazt38ekR+Hcbwo3u/6hARJ1nNRpAvF2zPrbUWj4y5GOH7QyP2n+YlcsqGs898Tv0qYjimdAw0PqR9t6lpTLr52xriizoC3XPN8QKypBRW9xxpSbK4o+Uh5volbKEJ5ilt8yKZ45eSVUKw2BLF52yDregSg2E7LpWoI0na/9xuOpkxgYbORlpGcrHCw3IU=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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This is dependent on the series [1]\nfor changing these property types to accept 'auto' values.\n\nAccelerated SMMUv3 Address Translation Services support is derived\nfrom IDR0, Range Invalidation support is derived from IDR3, Substream\nID size is derived from IDR1, and output address space is derived from\nIDR5.\n\nAdditionally, an OnOffAuto \"ats\" property is added for vfio-pci devices,\nwhere setting 'auto' detects the per-device presence of\nIOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED from the kernel, and the ATS cap can\nbe advertised or hidden by setting 'on' or 'off'. This is dependent\non Shameer's recent kernel series for reporting effective ATS support\nstatus [2].\n\nThe default values are set to 'auto' for all properties.\n\nA complete branch can be found here:\nhttps://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-resolve\n\nPlease take a look and let me know your feedback.\n\nThanks,\nNathan\n\n[0] https://lore.kernel.org/qemu-devel/20260309192119.870186-1-nathanc@nvidia.com/\n[1] https://lore.kernel.org/qemu-arm/20260323182454.1416110-1-nathanc@nvidia.com/\n[2] https://lore.kernel.org/all/20260317111603.101456-1-skolothumtho@nvidia.com/\n\nExample usage:\nqemu-system-aarch64 \\\n -object iommufd,id=iommufd0 \\\n -machine virt,accel=kvm,gic-version=3,ras=on,highmem-mmio-size=4T \\\n -cpu host -smp cpus=4 -m size=16G -nographic \\\n -object memory-backend-ram,size=16G,id=m0 \\\n -numa node,memdev=m0,cpus=0-3,nodeid=0 \\\n -numa node,nodeid=1 -numa node,nodeid=2 -numa node,nodeid=3 -numa node,nodeid=4 \\\n -numa node,nodeid=5 -numa node,nodeid=6 -numa node,nodeid=7 -numa node,nodeid=8 \\\n -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0,numa_node=0 \\\n -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1,accel=on,ats=auto,ssidsize=auto,ril=auto,oas=auto \\\n -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,io-reserve=0 \\\n -device vfio-pci-nohotplug,host=0009:06:00.0,bus=pcie.port1,rombar=0,id=dev0,iommufd=iommufd0,ats=auto \\\n -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=1 \\\n -object acpi-generic-initiator,id=gi1,pci-dev=dev0,node=2 \\\n -object acpi-generic-initiator,id=gi2,pci-dev=dev0,node=3 \\\n -object acpi-generic-initiator,id=gi3,pci-dev=dev0,node=4 \\\n -object acpi-generic-initiator,id=gi4,pci-dev=dev0,node=5 \\\n -object acpi-generic-initiator,id=gi5,pci-dev=dev0,node=6 \\\n -object acpi-generic-initiator,id=gi6,pci-dev=dev0,node=7 \\\n -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=8 \\\n -bios /usr/share/AAVMF/AAVMF_CODE.fd \\\n -device nvme,drive=nvme0,serial=deadbeaf1,bus=pcie.0 \\\n -drive file=/var/lib/libvirt/images/guest.qcow2,index=0,media=disk,format=qcow2,if=none,id=nvme0 \\\n -device e1000,romfile=/usr/local/share/qemu/efi-e1000.rom,netdev=net0,bus=pcie.0 \\\n -netdev user,id=net0,hostfwd=tcp::5558-:22,hostfwd=tcp::5586-:5586\n\nTesting:\nBasic sanity testing was performed on an NVIDIA Grace platform with GPU\ndevice assignment and running CUDA test apps on the guest. Observed the\nfeature properties being set based on host IOMMU capabilities and the\nATS capability for a vfio-pci device reported based on what was reported\nfrom the host. Verified that the VM boot will fail without a cold-plugged\ndevice, and that a hot-plugged device re-uses the resolved values from\nthe initial cold-plug. Additional testing and feedback are welcome.\n\nNathan Chen (11):\n hw/arm/smmuv3-accel: Add helper for resolving auto parameters\n hw/arm/smmuv3-accel: Implement \"auto\" value for \"ats\"\n hw/arm/smmuv3: Change the default ats support to match the host\n vfio/pci: Add ats property and mask ATS cap when not exposed\n hw/arm/smmuv3-accel: Implement \"auto\" value for \"ril\"\n hw/arm/smmuv3: Change the default ril support to match the host\n hw/arm/smmuv3-accel: Implement \"auto\" value for \"ssidsize\"\n hw/arm/smmuv3: Change the default ssidsize to match the host\n hw/arm/smmuv3-accel: Implement \"auto\" value for \"oas\"\n hw/arm/smmuv3: Change the default oas to match the host\n qemu-options.hx: Support \"auto\" for accel SMMUv3 properties\n\n backends/iommufd.c | 15 +++++++\n hw/arm/smmuv3-accel.c | 50 +++++++++++++++++++++++-\n hw/arm/smmuv3-accel.h | 2 +\n hw/arm/smmuv3.c | 61 +++++++++++++++++------------\n hw/core/machine.c | 8 ++++\n hw/vfio/pci.c | 63 ++++++++++++++++++++++++++++++\n hw/vfio/pci.h | 1 +\n include/hw/arm/smmuv3.h | 2 +\n include/system/host_iommu_device.h | 10 +++++\n qemu-options.hx | 1 -\n 10 files changed, 185 insertions(+), 28 deletions(-)" }