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{ "id": 2217937, "url": "http://patchwork.ozlabs.org/api/covers/2217937/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260331-t264-pwm-v4-0-c041659677cf@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260331-t264-pwm-v4-0-c041659677cf@nvidia.com>", "list_archive_url": null, "date": "2026-03-31T02:12:12", "name": "[v4,0/7] Tegra264 PWM support", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260331-t264-pwm-v4-0-c041659677cf@nvidia.com/mbox/", "series": [ { "id": 498119, "url": "http://patchwork.ozlabs.org/api/series/498119/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=498119", "date": "2026-03-31T02:12:15", "name": "Tegra264 PWM support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498119/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2217937/comments/", "headers": { "Return-Path": "\n <linux-tegra+bounces-13447-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=eU4eEqjG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=37uCpLWqPlXVN7F/G1DOY8UA28+L+hols+4SBM4yLh8=;\n b=eU4eEqjG6WIH2nDfRkpKy17FtJEjZBRdGOjN7zaauV8+UguQSZQz2WCgTaaVCUiCRxLFkMG/7R+UTsvMrZlQKJvOW56ik9sD4xqVTDGkmaSN5oNjJ4plfzI7staTFivxarYRN84tnbzYbkgKV8RMuTyp88HM4wJ6RsYbJXthuGg2loV2/87x5pNUbsXZXXJbYg4lwf7W/L5JKFfC1jxNjmqIvloarQ8gH8hdbDtou87aNhDs5KhdVgQTDNMpiJ5zRxeOpqUn0BUXW68Bxhjn4EXDE3jBQPuipM6pRxKDFmvfgePU6Jz5cXp/Pq9qwvUPvvSL8TQGX2mP77YZDfhNlg==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Subject": "[PATCH v4 0/7] Tegra264 PWM support", "Date": "Tue, 31 Mar 2026 11:12:12 +0900", "Message-Id": "<20260331-t264-pwm-v4-0-c041659677cf@nvidia.com>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "X-B4-Tracking": "v=1; b=H4sIAAAAAAAC/2XMTQ6CMBCG4auQrq2Z/lHqynsYF0hbmYVAWlI1h\n LtbiIsal99knnch0QV0kZyqhQSXMOI45CEPFen6drg7ijZvwoHXIEDQmdeSTs8HVdoxsCCM9Yz\n k9yk4j689dbnm3WOcx/Dey4lt12+EF5HEKFDZSe+1FKDAn4eEFttjNz7IVkm8lKqQPEtjGts0y\n jTyJv6kKKSAQooslWZScm2V0fWPXNf1A3G1+WIVAQAA", "X-Change-ID": "20260303-t264-pwm-57e10d039df1", "To": "Thierry Reding <thierry.reding@gmail.com>, =?utf-8?q?Uwe_Kleine-K=C3=B6n?=\n\t=?utf-8?q?ig?= <ukleinek@kernel.org>,\n Jonathan Hunter <jonathanh@nvidia.com>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Thierry Reding <treding@nvidia.com>,\n Mikko Perttunen <mperttunen@nvidia.com>, Yi-Wei Wang <yiweiw@nvidia.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "TYWP286CA0029.JPNP286.PROD.OUTLOOK.COM\n (2603:1096:400:262::17) To SJ2PR12MB9161.namprd12.prod.outlook.com\n (2603:10b6:a03:566::20)", "Precedence": "bulk", "X-Mailing-List": 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"=?utf-8?q?o7tPP+wmjZOTZ12upuwbGY2I7uho?=\n\t=?utf-8?q?KpnCkzKwR0zeCm/9dJwA7D1EJH9/fTyHfAjYLU0sTDqMQczA0/+2TWgqEcpFOoMpd?=\n\t=?utf-8?q?ryoRtDkIOo+HiLf7j58Lyt2pM/kUs4dywtHQxOfjayFUcVa+gKKNai7xYbi8d/1EW?=\n\t=?utf-8?q?IdGGKS4E3/iZRppgK+NaXTE84smUpFt81HwJ8uhfwSgzhuCWc4g6So7gOVYYA3ho5?=\n\t=?utf-8?q?bWr+DVqahnBz2IqqUr0JaGRSmPf9I7YkP05kMfIZ4KFkEBEluAVz46l0EDBo03Jhh?=\n\t=?utf-8?q?XPBb48Qoil7XPNqttTSJvZzzHwlD049T97fXidR8wVRYJ2jZGKTI5sVv5sX3f7lmI?=\n\t=?utf-8?q?e3R4UexzKzp++bZiZRcVomzlUjDLh2ghF3xR0zlAvLGiOqz3OeLiN2ycif1sMawbU?=\n\t=?utf-8?q?+x8xYhm2zH3h+bphthRpbGbgeVvySyH9+zjM3s9BtTJ5pGZ/ZMbDUXw7CI8b+sAOs?=\n\t=?utf-8?q?w8C4fLRRJdMrZiLdoJHnuyiUeJdl65usUnBx0sjKzHlzUItiM6l8SPiyicaCAgtKE?=\n\t=?utf-8?q?oZLMU294ny/fedSkMRyJa1DTK0bZvgNGTP0PY4m//foRzBCl33qHrJNyYRVw3Bgk9?=\n\t=?utf-8?q?Lbs/ovr/MzY2im4RakthN4e3ulOFTBMygCAGLbxmnVvv1glrYH0C+pOevm8tzirEz?=\n\t=?utf-8?q?+6o58Sv6CdydUTDiHDZTXEgcPwIkGxdJmMHHdspFWJN5I/Uupygjw6fycpI5L39vf?=\n\t=?utf-8?q?TYX5Ezt4s626fs3EovzQ/kMis4uMwRoQs7mRVu2jxbwITMsLvzYhINRcuYo+zVa/B?=\n\t=?utf-8?q?W54EwiUYhzlK/yIbrhqEpQIy1+k6vwLtq65w8CjBgIGof4o6VDEiWDbACOshugMTJ?=\n\t=?utf-8?q?VLYoGkCIWVU86UZ70ts5mrILzER/UKhnPv8L3sbC+xYFEIjIW91ksk1ro0dfMRUYJ?=\n\t=?utf-8?q?ZHdAmQHJuIyyDif4fhU2/vPRmrWKUIzQnpEcbSQf3GyEL3O7gR+CzXhHlITgdcymz?=\n\t=?utf-8?q?1pw3Ki0Uc0KqpI8J3blI13T8gw1pdZGqdgTgkY06HK0fmzcjTOzZeFvf1Pid/JRJQ?=\n\t=?utf-8?q?xXriolMvNcWfcPWzMHgR9xFJuHYLMU0pGolpL4jxPJpF1cYvozF5Bu5vh3b5ZL/Yj?=\n\t=?utf-8?q?UvT5Z2QqFygyjsRoS7XAHjx0dqOgRdI31WyV80Frn21UQuNtQw7jiRRrB5ci2U0Im?=\n\t=?utf-8?q?n/IiDx4uKTQR1b30qOfQ/E4bvgkPtYqsg+ePjwMUzw08Idq8fH5AjbvmuvbE+PGPJ?=\n\t=?utf-8?q?4+2F4IT3kWAd4JwsnBYwe/bipBN8MhmGMlqf6EzQO4IOTPFv9t7FSjWWgeQVm/gUc?=\n\t=?utf-8?q?+bWL5lx4GORsvSrbXD1uWJQQhdMU6bizjKi3Z7IFJc1esSxKHdiN/Tfn4iJXhEevg?=\n\t=?utf-8?q?+ERd3ps9Sr5SvkbhNX5Iz5g9l3jPKSt2K4MFaN1vYh7GrxX1IGA/uhxwwLpPMoljG?=\n\t=?utf-8?q?EkiGkc2P6fjWIPQLWU4mKBEDZLabMBhs+3HSIXsZ8jIwKJh0teN/aG+tH0V70CdY0?=\n\t=?utf-8?q?9dFvZnR9DBvuh8iUBB0f8FMKfeVbQcg2MHXDt0ABjA9x0FZePtt78YMN6wYbFbJSj?=\n\t=?utf-8?q?SB5Zd+0KLmuePCZozycl9N2J/PTViDRZmVR6HDeK7TA7rd6sFdI0KL/Llnt33+H7e?=\n\t=?utf-8?q?MB3NDqyaTBJiX01hCiWtXEcHLTU5Nt2eFK8j/hopiEXTZ1QBr4ZR4LMop09wx8OiJ?=\n\t=?utf-8?q?jZD9AcEPvff4Tvjt8lys+uDbkyNsWDSakveBacRrYK2OvOlClKEqPUm7fA0WCQs7t?=\n\t=?utf-8?q?5q5+MBt/TItGK1/zk?=", "X-MS-Exchange-AntiSpam-MessageData-1": "wmUOuF/cOYpckA==", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 49ce0acc-0219-4388-c879-08de8ecaf653", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "31 Mar 2026 02:12:30.2182\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n EUgf+WHxLPT2eVesHYU5nqG6nSrvudP+/5OYhgT2+yOOm8lkBfb/DNM1npQydNBBhLovdlsANWw+uY1Jh1UUYg==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB8330" }, "content": "Hello,\n\nthis adds support for the PWM controller on Tegra264. The controller\nis similar to previous generations, but the register fields are\nwidened, the depth is made configurable, and the enable bit moves\nto a different spot.\n\nThis series adds only basic support with fixed depth -- configurable\ndepth will come later.\n\nPatch 1 adds device tree bindings for Tegra264 PWM (compatible\n string).\n\nPatches 2 to 6 contain the PWM driver changes.\n\nPatch 7 adds device tree nodes for the PWM controllers on Tegra264.\n\nThanks,\nMikko\n\n---\nChanges in v4:\n- Use ULONG_MAX rather than S64_MAX to avoid overflow on 32-bit platforms\n- Link to v3: https://lore.kernel.org/r/20260330-t264-pwm-v3-0-5714427d5976@nvidia.com\n\nChanges in v3:\n- Fixed device tree binding patch.\n- Picked up trailers.\n- Link to v2: https://lore.kernel.org/r/20260325-t264-pwm-v2-0-998d885984b3@nvidia.com\n\nChanges in v2:\n- Added device tree binding and Tegra264 device tree patches by Thierry.\n- Link to v1: https://lore.kernel.org/r/20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com\n\n---\nMikko Perttunen (4):\n pwm: tegra: Modify read/write accessors for multi-register channel\n pwm: tegra: Parametrize enable register offset\n pwm: tegra: Parametrize duty and scale field widths\n pwm: tegra: Add support for Tegra264\n\nThierry Reding (2):\n dt-bindings: pwm: Document Tegra264 controller\n arm64: tegra: Add PWM controllers on Tegra264\n\nYi-Wei Wang (1):\n pwm: tegra: Avoid hard-coded max clock frequency\n\n .../bindings/pwm/nvidia,tegra20-pwm.yaml | 1 +\n arch/arm64/boot/dts/nvidia/tegra264.dtsi | 72 +++++++++++\n drivers/pwm/pwm-tegra.c | 141 ++++++++++++++-------\n 3 files changed, 171 insertions(+), 43 deletions(-)\n---\nbase-commit: 11439c4635edd669ae435eec308f4ab8a0804808\nchange-id: 20260303-t264-pwm-57e10d039df1" }