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{ "id": 2217780, "url": "http://patchwork.ozlabs.org/api/covers/2217780/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260330144456.13551-1-akhilrajeev@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330144456.13551-1-akhilrajeev@nvidia.com>", "list_archive_url": null, "date": "2026-03-30T14:44:46", "name": "[v5,00/10] Add GPCDMA support in Tegra264", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260330144456.13551-1-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 498044, "url": "http://patchwork.ozlabs.org/api/series/498044/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=498044", "date": "2026-03-30T14:44:52", "name": "Add GPCDMA support in Tegra264", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/498044/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2217780/comments/", "headers": { "Return-Path": "\n <linux-tegra+bounces-13421-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=D9/BoSDU;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>, Rob Herring\n\t<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley\n\t<conor+dt@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, \"Jonathan\n Hunter\" <jonathanh@nvidia.com>, Laxman Dewangan <ldewangan@nvidia.com>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>, <dmaengine@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "Akhil R <akhilrajeev@nvidia.com>", "Subject": "[PATCH v5 00/10] Add GPCDMA support in Tegra264", "Date": "Mon, 30 Mar 2026 20:14:46 +0530", "Message-ID": "<20260330144456.13551-1-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MN1PEPF0000ECD8:EE_|LV2PR12MB6013:EE_", "X-MS-Office365-Filtering-Correlation-Id": "e1156f02-65ec-47b6-c9ba-08de8e6b028b", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|1800799024|36860700016|7416014|376014|921020|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\tQvyGY+X31k2mvSaRpDmsgFrCL0Wrclu4C8T8oyNJruWOReCXVfRyT3uIHZV1JhcUpHFiq9xTIPX0RkSs3+Yu1OOH2bA2PLQ/j/YM44vT5SrV0gy3qdPIE+FHIGR7HvuUS6bvFfDkcEPUMuPwCp3w0w9dYPaPwZ5GuBOjqF+FjCqE0vRaqFDBHWqVVS5O5pre2SL77pgo5puC8b3cq1A3nGsWLQDpexGQbY6anU2is0NLWJ/UIQXioGz4wU+BIQ+JtBX3MJZAt9eXuHwd91e2/58adL9SHgyXyEomr0+Xa+8eDSvEQzZOwuXIPWcUHnou3+62xHKjekInuic4seP73ZWWq5BIqX5r6KRMtIR572mbTOvso/+BFe68xQ/mhDaXh8Yxiy8pXsNYtOEEiKBFYdtIepK9ajjbT65XL2RfkK/Jxe00OdkxaTkFjXn8RUWJAeHDLwcRbFiVzLdLKWjm45ORsuCptrIcP7sChySiHYlk6YdPD4o0sG9H1BrZ/H37Md/sOkLHbkUgtG4bG+cfBMyWiuWxybsCZu6jx2R7j10xPLhQUWAkH9bGHbW7pPeB+38lg/HB6zltvTyHO0fiCbwJae8WJh5dexqOACbIxhju21WS0pLgkb0Z3je+4E3RKm1bbHZ1ui9pJdkfDaKxW7u4ms7p2gzGe1RH5Tb/pSBywk7BfoY5gErNtIZkmDwha8Mp6rTgdtNDybRI3UeHArTkPZ+xleXrQ5G3W7AjI96u3+OtUz9YpUgGfXOCmHNA/75LUL0jhJTOzxYtNXu0+uywEITxoRX8ha5i+Fr1zYSSPHtCzzAWIfyqJWAaVfGw", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(7416014)(376014)(921020)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t9npI7aEpyqlGg12J8tIZ4m3eR4RxUGLmAmtjub9nj3AalPoSkPkW9D8hhj4XUcO03cNde5Pem1HBtCQ/4fXKnCsYjsPmEAUNWU5MOJQevd6ovBNqf/pkFjbnQNrODu31X4DFsVNWX/rK+/JJc44RfRWy1bK0mhoEVSm8+P+fnI4Mc5+8AqrzVKKLNIyJYYLlMSo0drpsO2pkIoWTCYZ+cJcZyNlud5Pp6oS35v7B2WRsItDnwt5BEPG4or9d5uWdvjrsWv+9kxALSUdXNGdU7V21uBlKd+2hDnbEmDzMJ8n94Pe7fDBmKoxPKe4SZPITnXKYyeNmxwtbXFbtt/+WHR5Fy74FKOnkK3kb/tlvCfgWuvNespAgxtXfyVZ/AYiR4TodzEw7ZAygCe4TJPHsLkVCLu9CgDf/qkzsZ0y9G0/GZB0B+4xKciFno9AwL8k/", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Mar 2026 14:45:38.6728\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e1156f02-65ec-47b6-c9ba-08de8e6b028b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tMN1PEPF0000ECD8.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB6013" }, "content": "This series adds support for GPCDMA in Tegra264 with additional\nsupport for separate stream ID for each channel. Tegra264 GPCDMA\ncontroller has changes in the register offsets and uses 41-bit\naddressing for memory. Add changes in the tegra186-gpc-dma driver\nto support these.\n\nv4->v5:\n- Use dev_err_probe() when returning error from the probe function.\n- Remove tegra194 and tegra234 compatible from the reset 'if' condition\n in the bindings as suggested in v2 (which I missed).\nv3->v4:\n- Split device tree changes to two patches.\n- Reordered patches to have fixes first.\n- Added fixes tag to dt-bindings and device tree changes.\nv2->v3:\n- Add description for iommu-map property and update commit descriptions.\n- Use enum for compatible string instead of const.\n- Remove unused registers from struct tegra_dma_channel_regs.\n- Use devm_of_dma_controller_register() to register the DMA controller.\n- Remove return value check for mask setting in the driver as the bitmask\n value is always greater than 32.\nv1->v2:\n- Fix dt_bindings_check warnings\n- Drop fallback compatible \"nvidia,tegra186-gpcdma\" from Tegra264 DT\n- Use dma_addr_t for sg_req src/dst fields and drop separate high_add\n variable and check for the addr_bits only when programming the\n registers.\n- Update address width to 39 bits for Tegra234 and before since the SMMU\n supports only up to 39 bits till Tegra234.\n- Add a patch to do managed DMA controller registration.\n- Describe the second iteration in the probe.\n- Update commit descriptions.\n\nAkhil R (10):\n dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional\n arm64: tegra: Remove fallback compatible for GPCDMA\n dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property\n dmaengine: tegra: Make reset control optional\n dmaengine: tegra: Use struct for register offsets\n dmaengine: tegra: Support address width > 39 bits\n dmaengine: tegra: Use managed DMA controller registration\n dmaengine: tegra: Use iommu-map for stream ID\n dmaengine: tegra: Add Tegra264 support\n arm64: tegra: Enable GPCDMA in Tegra264 and add iommu-map\n\n .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 32 +-\n .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 4 +\n arch/arm64/boot/dts/nvidia/tegra264.dtsi | 3 +-\n drivers/dma/tegra186-gpc-dma.c | 433 +++++++++++-------\n 4 files changed, 288 insertions(+), 184 deletions(-)" }