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{ "id": 2217557, "url": "http://patchwork.ozlabs.org/api/covers/2217557/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/cover/20260330-andes-pwm-v5-0-01c59a659d2c@andestech.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260330-andes-pwm-v5-0-01c59a659d2c@andestech.com>", "list_archive_url": null, "date": "2026-03-30T07:45:42", "name": "[v5,0/3] pwm: add support for Andes platform", "submitter": { "id": 92477, "url": "http://patchwork.ozlabs.org/api/people/92477/?format=api", "name": "Ben Zong-You Xie via B4 Relay", "email": "devnull+ben717.andestech.com@kernel.org" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/cover/20260330-andes-pwm-v5-0-01c59a659d2c@andestech.com/mbox/", "series": [ { "id": 497968, "url": "http://patchwork.ozlabs.org/api/series/497968/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=497968", "date": "2026-03-30T07:45:42", "name": "pwm: add support for Andes platform", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/497968/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2217557/comments/", "headers": { "Return-Path": "\n <linux-pwm+bounces-8405-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=ZLE0g4ON;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774856745; cv=none;\n b=dEo34vRI2qEfp/3CR7ShyngUOXYTsLDyGMqYI7xd86zvL0dSN7E90sZRKRnUitxflhlynbu2etgRBhJYszkJgMbNxSQcME4bKJlQrU/zvL2BpUTduKLdD1kEX3yUsxDl8ena2eIijczob0RF3U0BVBECPj7nqL8UR4fqVQrFbuo=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774856745; c=relaxed/simple;\n\tbh=7Fo3jVCC8hwVStRvGW0Q1tYK6679IPrcIgWpjNA/zQc=;\n\th=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc;\n b=KCLtR6UpjGyKHaVRZ2d0UKDgd9biirawsfVVXDbbiX9OCiDtQJzE1pOrY7CbIXAO0p6JkE761NzirUgTZjw6WDfLVPBCD+fVvw7z8mJmslOZRSVcbajbg4NXcK8I1+GJ4XRAV7pPlEfjauQ8nRGoJn+HtHFy+TNLp0bjFDeYB/o=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=ZLE0g4ON; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774856745;\n\tbh=7Fo3jVCC8hwVStRvGW0Q1tYK6679IPrcIgWpjNA/zQc=;\n\th=From:Subject:Date:To:Cc:Reply-To:From;\n\tb=ZLE0g4ONVGsyFGRxsfoKGTVUpR4xapqWvLdpJQivjod6U7Mjb4CtXEZix1KlD4VYt\n\t 4kMi4j/Z1tGmF4zxB9Fc4LhMAhortUDFYAgrDUoFmJVgqzKkk36/xD6sVTv37E/CDg\n\t zj9i7goZeRNkrog5NXThCBGOO9yu0V5M70RIor8nv7Leos2vR7GtsyEP4/S6bskyWL\n\t ODmJ+00f0kbt3HLvxyz/aU9UEgNTOjqnePGHSsavNl28dSqV4UhSSwXfRN7zCw20Pf\n\t /lcvlK275MAg4dWg84KoIsiFF48+8/zxY3r7vg+pMI1Hhsl/PGV9MQrRgCSPELCT5/\n\t 2DUJHvMnds5dg==", "From": "Ben Zong-You Xie via B4 Relay <devnull+ben717.andestech.com@kernel.org>", "Subject": "[PATCH v5 0/3] pwm: add support for Andes platform", "Date": "Mon, 30 Mar 2026 15:45:42 +0800", "Message-Id": "<20260330-andes-pwm-v5-0-01c59a659d2c@andestech.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "X-B4-Tracking": "v=1; b=H4sIACYqymkC/32QwWrDMAyGX6X4PAdJtuVkp73H2CFx1caDJiXOs\n o2Sd6+dUgo99CDBD//3CXRRSaYoSb3vLmqSJaY4Djm4t50KfTscRcd9zoqAGAisboe9JH3+PWk\n EaZkRgwkHlfvnSQ7xb3N9ft1y+um+JcxFUBp9TPM4/W/HFiy94rUIVOfxhBU2jFQ3GnUng0f/s\n Z2bJfRVGE+qaBd6gHkBA1pfIXkkti9BcwcdIBlsjDO2qr0lxy85e+eeP7BYDZo9IHcdGufcM72\n u6xUCeadEYgEAAA==", "X-Change-ID": "20260204-andes-pwm-10ea6611c3cf", "To": "=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, Ben Zong-You Xie <ben717@andestech.com>", "X-Mailer": "b4 0.15-dev-47773", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1774856744; l=3420;\n i=ben717@andestech.com; s=20260120; h=from:subject:message-id;\n bh=7Fo3jVCC8hwVStRvGW0Q1tYK6679IPrcIgWpjNA/zQc=;\n b=AjO4pcGgOeZO6/wJevhW4+mYZ4WFVj7fGjv6oHVG3RMT4n07LkN/Enq3OVwJ/xTkCGB7T9FSb\n wGZvW9/8+sdAwamFfCKrfpGQECuRCYWgl2CrG3Z30Z+tUVdLzS8OAcm", "X-Developer-Key": "i=ben717@andestech.com; a=ed25519;\n pk=nb8L7zQKGJpYk0yvrYKjViOZ34A36g1ZIsCmCsP518s=", "X-Endpoint-Received": "by B4 Relay for ben717@andestech.com/20260120 with\n auth_id=610", "X-Original-From": "Ben Zong-You Xie <ben717@andestech.com>", "Reply-To": "ben717@andestech.com" }, "content": "The ATCPIT100 is a set of compact multi-function timers, which can be\na simple timer or PWM, or a combination of the timer and the PWM. This\nIP block is a core component of the Andes AE350 platform, which serves\nas a reference architecture for SoC designs. The QiLai SoC also\nintegrates this controller.\n\nThis device driver was previously part of the Linux Kernel, and the\ncompatible was its IP name \"andestech,atcpit100\". However, the driver\nand its binding were removed due to the deprecation of the NDS32\narchitecture [1]. Although Andes now dedicates our effort on RISC-V,\nATCPIT100 is still one of our peripheral IPs, and that's why we are\nre-introducing it now. Since only using the IP block name as the\ncompatible is forbidden now, change the compatible to\n\"andestech,ae350-pwm\" and \"andestech,qilai-pwm\".\n\n[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=aec499c75cf8e0b599be4d559e6922b613085f8f\n\nSigned-off-by: Ben Zong-You Xie <ben717@andestech.com>\n---\nChanges in v5:\n- Rebased on ukleinek/pwm/for-next\n- (1/4)\n - Added Rob's reviewed-by tag.\n- Link to v4: https://patch.msgid.link/20260204-andes-pwm-v4-0-67016bb13555@andestech.com\n\nChanges in v4:\n- Updated cover letter title and its commit message.\n- (1/3)\n - Updated the compatibles and the binding file name.\n - Added the description to the binding.\n - Corrected device register size.\n - Dropped the changes to the MAINTAINERS file.\n- (2/3)\n - Updated the driver name.\n - Made the driver support inversed polarity.\n - Changed the clock selection algorithm.\n - Made the configuration depend on ARCH_ANDES, instead of RISCV. (Krzysztof)\n - Dropped the changes to the MAINTAINERS file.\n- (3/3) (new)\n - Collected all changes to the MAINTAINERS file into a single patch.\n- Link to v3: https://patch.msgid.link/20250123193534.874256-1-ben717@andestech.com\n\nChanges in v3:\n- (1/2):\n - modified the compatible string. (Krzysztof)\n- (2/2):\n - added a check for the clock rate to prevent the overflow warning.\n (kernel test robot)\n - removed the unnecessary check in .apply(). (kernel test robot)\n- Link to v2: https://patch.msgid.link/20241202060147.1271264-1-ben717@andestech.com\n\nChanges in v2:\n- (1/2):\n - changed \"title\" in the yaml file.\n - removed vendor-specific property, and added clocks property.\n- (2/2):\n - added a description for hardware limitations. (Uwe)\n - switched the clock parent depending on the requested setting\n instead of statically configuring the clock source in DT. (Uwe)\n- Link to v1: https://patch.msgid.link/20241028102721.1961289-1-ben717@andestech.com\n\n---\nBen Zong-You Xie (3):\n dt-bindings: pwm: add support for AE350 PWM controller\n pwm: add Andes PWM driver support\n MAINTAINERS: add an entry for Andes PWM driver\n\n .../bindings/pwm/andestech,ae350-pwm.yaml | 61 ++++\n MAINTAINERS | 6 +\n drivers/pwm/Kconfig | 10 +\n drivers/pwm/Makefile | 1 +\n drivers/pwm/pwm-andes.c | 306 +++++++++++++++++++++\n 5 files changed, 384 insertions(+)\n---\nbase-commit: aa8f35172ab66c57d4355a8c4e28d05b44c938e3\nchange-id: 20260204-andes-pwm-10ea6611c3cf\n\nBest regards,\n-- \nBen Zong-You Xie <ben717@andestech.com>" }