Cover Letter Detail
Show a cover letter.
GET /api/covers/2216864/?format=api
{ "id": 2216864, "url": "http://patchwork.ozlabs.org/api/covers/2216864/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/cover/20260327-ad4692-multichannel-sar-adc-driver-v5-0-11f789de47b8@analog.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327-ad4692-multichannel-sar-adc-driver-v5-0-11f789de47b8@analog.com>", "list_archive_url": null, "date": "2026-03-27T11:07:56", "name": "[v5,0/4] iio: adc: ad4691: add driver for AD4691 multichannel SAR ADC family", "submitter": { "id": 92791, "url": "http://patchwork.ozlabs.org/api/people/92791/?format=api", "name": "Radu Sabau via B4 Relay", "email": "devnull+radu.sabau.analog.com@kernel.org" }, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/cover/20260327-ad4692-multichannel-sar-adc-driver-v5-0-11f789de47b8@analog.com/mbox/", "series": [ { "id": 497747, "url": "http://patchwork.ozlabs.org/api/series/497747/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=497747", "date": "2026-03-27T11:07:57", "name": "iio: adc: ad4691: add driver for AD4691 multichannel SAR ADC family", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/497747/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2216864/comments/", "headers": { "Return-Path": "\n <linux-gpio+bounces-34255-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=AT4GCK+J;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-34255-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"AT4GCK+J\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhycn0VSYz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:11:05 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id CE0163012EA2\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 11:08:57 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 72E483E7173;\n\tFri, 27 Mar 2026 11:08:11 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id E83B23E4C9C;\n\tFri, 27 Mar 2026 11:08:07 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPS id 3795AC2BC86;\n\tFri, 27 Mar 2026 11:08:07 +0000 (UTC)", "from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id 216FE10ED64A;\n\tFri, 27 Mar 2026 11:08:07 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774609688; cv=none;\n b=AGhzdoMTvxx8uma6NNj0E8CCU8R+u3IHiZuCQNLoFvB9PnEPERGCsb0HQ1rg9T+CswTAeYGH/PMPHTGy3b67uxKT45yIgVXoQhwaOvY6JUhSmELB5aIC8l8mJSxcWPrakrSri+sdny9Hi1e9IPFBWMRLVeyPeYR5VfPlFcgAMgY=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774609688; c=relaxed/simple;\n\tbh=WVehT+IHIA/FSGO2VDSTliaZHBQNzs6pbxw+M17zNHE=;\n\th=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc;\n b=SGkvaFGCKJet7345JRS6Muln2bItd6IrsHs50tIGeWNl3XSoKOTljbX4OGSHvphFYABiS/MQwCnIm6RJpSYXjETbrbSIr/VQ8IGtRdLk9+V9Lx5bwIzPZfy+9ohMXc0iuXg6XH8iXt6PcQsRwl76F7S4dY8ccRhyPQnUjrxnE+E=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=AT4GCK+J; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774609687;\n\tbh=WVehT+IHIA/FSGO2VDSTliaZHBQNzs6pbxw+M17zNHE=;\n\th=From:Subject:Date:To:Cc:Reply-To:From;\n\tb=AT4GCK+Jt4Vg2VHAGFmGQKDUmrXDcKfJ9IsS3Xb/huKx5Fk/liw2b4xRa1nlDlltT\n\t MlWUD6Z5+ffoOFLibkq3ovQZjPvS7/nMSh0m0bzqJ9b/T4l1RiP0ZahPZUym2lfd8K\n\t cr6T1j/ccSHldb7BgcexWJSV57F7t2zgIrRZcfCqlN9QETIvEcX501NMaZ/T1//Cvx\n\t mFe+1AzfDggwKWNutEaFSa/2aWhxTAE2m+rQRghoQvqlEQ4QhUtSS0YOVmpPw8L78V\n\t 0ln/JCU6Vl02OnGu9ZGYSIWJtF8O2gcKUVlFqMN8aDQZ2+p08YOl9TZMDMZfbWFpmy\n\t R+jm4FhsrFZTQ==", "From": "Radu Sabau via B4 Relay <devnull+radu.sabau.analog.com@kernel.org>", "Subject": "[PATCH v5 0/4] iio: adc: ad4691: add driver for AD4691\n multichannel SAR ADC family", "Date": "Fri, 27 Mar 2026 13:07:56 +0200", "Message-Id": "\n <20260327-ad4692-multichannel-sar-adc-driver-v5-0-11f789de47b8@analog.com>", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "X-B4-Tracking": "v=1; b=H4sIAAxlxmkC/43Oz2rDMAwG8FcpPs/DluXE2WnvUXbwH601pMmwO\n 9NR8u5TCoOMXoJO34f4SXdRqWSq4u1wF4VarnmeONiXg4hnP51I5sRZgIJOGQXSJ+wGkJfv8Zr\n XjYlGWX3hPspUcqMie0eYEBNgAMHQV6HPfHscOX5wPud6ncvP42bTa/vH2z1801JJYzqAwbsUY\n //uJz/Op9c4X8TqN9iYWu0ygc00hOA8BUv62TRb0+wyDZsBk8bktNdOP5m4MWHfn8imshC1sjy\n 9/2cuy/ILkPyAmdEBAAA=", "X-Change-ID": "20260302-ad4692-multichannel-sar-adc-driver-78e4d44d24b2", "To": "Lars-Peter Clausen <lars@metafoo.de>,\n Michael Hennerich <Michael.Hennerich@analog.com>,\n Jonathan Cameron <jic23@kernel.org>, David Lechner <dlechner@baylibre.com>,\n\t=?utf-8?q?Nuno_S=C3=A1?= <nuno.sa@analog.com>,\n Andy Shevchenko <andy@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Liam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>,\n Linus Walleij <linusw@kernel.org>, Bartosz Golaszewski <brgl@kernel.org>,\n Philipp Zabel <p.zabel@pengutronix.de>, Jonathan Corbet <corbet@lwn.net>,\n Shuah Khan <skhan@linuxfoundation.org>", "Cc": "linux-iio@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org,\n linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org,\n Radu Sabau <radu.sabau@analog.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1774609685; l=10360;\n i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id;\n bh=WVehT+IHIA/FSGO2VDSTliaZHBQNzs6pbxw+M17zNHE=;\n b=F6+j2C82xzjHQhYi5aDuklQz6J3utIZOO99CHsddkQ/6q4sxYjZmPrcg2Cu3RrlCDi7Pt8hQW\n TaIPl4+o0KMDeTGFnZtmj2aAauNmcoYAGsa6UzCs9bjr+8IaCN3bYY3", "X-Developer-Key": "i=radu.sabau@analog.com; a=ed25519;\n pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU=", "X-Endpoint-Received": "by B4 Relay for radu.sabau@analog.com/20260220 with\n auth_id=642", "X-Original-From": "Radu Sabau <radu.sabau@analog.com>", "Reply-To": "radu.sabau@analog.com" }, "content": "This series adds support for the Analog Devices AD4691 family of\nhigh-speed, low-power multichannel successive approximation register\n(SAR) ADCs with an SPI-compatible serial interface.\n\nThe family includes:\n - AD4691: 16-channel, 500 kSPS\n - AD4692: 16-channel, 1 MSPS\n - AD4693: 8-channel, 500 kSPS\n - AD4694: 8-channel, 1 MSPS\n\nThe devices support two operating modes, auto-detected from the device\ntree:\n - CNV Burst Mode: external PWM drives CNV independently of SPI;\n DATA_READY on a GP pin signals end of conversion\n - Manual Mode: CNV tied to SPI CS; each SPI transfer reads\n the previous conversion result and starts the\n next (pipelined N+1 scheme)\n\nA new driver is warranted rather than extending ad4695: the AD4691\ndata path uses an accumulator-register model — results are read from\nAVG_IN registers, with ACC_MASK, ADC_SETUP, DEVICE_SETUP, and\nGPIO_MODE registers controlling the sequencer — none of which exist\nin AD4695. CNV Burst Mode (PWM drives CNV independently of SPI) and\nManual Mode (pipelined N+1 transfers) also have no equivalent in\nAD4695's command-embedded single-cycle protocol.\n\nThe series is structured as follows:\n 1/4 - DT bindings (YAML schema) and MAINTAINERS entry\n 2/4 - Initial driver: register map via custom regmap callbacks,\n IIO read_raw/write_raw, both operating modes, single-channel\n reads via internal oscillator (Autonomous Mode)\n 3/4 - Triggered buffer support: IRQ-driven (DATA_READY on a GP pin\n selected via interrupt-names) for CNV Burst Mode; external IIO\n trigger for Manual Mode to handle the pipelined N+1 SPI protocol\n 4/4 - SPI Engine offload support: DMA-backed high-throughput\n capture path using the SPI offload subsystem\n\nDatasheets:\n https://www.analog.com/en/products/ad4691.html\n https://www.analog.com/en/products/ad4692.html\n https://www.analog.com/en/products/ad4693.html\n https://www.analog.com/en/products/ad4694.html\n\nSigned-off-by: Radu Sabau <radu.sabau@analog.com>\n---\nChanges in v5:\n- Reorder datasheets numerically\n- Fix interrupt-names: use enum with minItems/maxItems\n- Remove if/then block requiring interrupts — driver detail, not hardware constraint\n- Remove redundant .shift = 0 from channel macro\n- Write max_rate comparison as 1 * HZ_PER_MHZ\n- Invert set_sampling_freq loop to use continue\n- Fix fsleep() line break; remove blank line in read_raw\n- Reorder supply init: vio immediately after avdd\n- Move comment rewrites and OSC_FREQ_REG condition into the base driver patch\n- Add bit-15 READ comment in reg_read\n- Rewrite ldo-in handling with cleaner if/else-if pattern\n- Drop redundant refbuf_en = false; invert if (!rst) in reset\n- Drop reset_control_assert() — GPIO already asserted at probe\n- Use regmap_update_bits/assign_bits in config\n- Remove tab-column alignment of state struct members\n- Declare osc_freqs[] as const int, eliminating explicit casts\n- Drop obvious AUTONOMOUS mode comment\n- Rename ACC_COUNT_LIMIT → ACC_DEPTH_IN to match datasheet\n- Use bitmap_weight()/bitmap_read() for active_scan_mask access;\n add #include <linux/bitmap.h>\n- Fix channel macro line-continuation tab alignment\n- Use IIO_CHAN_SOFT_TIMESTAMP(8) for 8-channel variants\n- Use aligned_s64 ts in scan struct\n- Add comment explaining start-index removal in set_sampling_freq\n- Remove trailing comma after NULL in buffer_attrs[]\n- Add IRQF_NO_AUTOEN rationale comment\n- Remove unreachable manual_mode guards in sampling_frequency_show/store\n- Remove st->trig; use indio_dev->trig directly\n- Move max_speed_hz param to the offload patch where it is used\n- Use DIV_ROUND_UP for CNV period; use compound pwm_state initializer\n- Move offload fields into a separately allocated sub-struct\n- Build TX words via u8* byte-fill; fixes sparse __be32 warnings\n- Add three scan types (NORMAL/OFFLOAD_CNV/OFFLOAD_MANUAL) with\n get_current_scan_type; triggered buffer path uses storagebits=16\n- Fix IIO_CHAN_INFO_SCALE: use iio_get_current_scan_type() for realbits\n- Add MODULE_IMPORT_NS(\"IIO_DMAENGINE_BUFFER\")\n- Add Documentation/iio/ad4691.rst\n- Link to v4: https://lore.kernel.org/r/20260320-ad4692-multichannel-sar-adc-driver-v4-0-052c1050507a@analog.com\n\nChanges in v4:\n- dt-bindings: add avdd-supply (required) and ldo-in-supply (optional);\n rename vref-supply → ref-supply, vrefin-supply → refin-supply;\n corrected reset-gpios polarity (active-high → active-low); remove\n clocks and pwm-names; extend interrupts to up to 4 GP pins with\n interrupt-names \"gp0\"..\"gp3\"; reduce #trigger-source-cells to\n const: 1 (GP pin number); add gpio-controller / #gpio-cells = <2>;\n drop adi,ad4691.h header; update binding examples\n- driver: rename CNV Clock Mode → CNV Burst Mode throughout\n- driver: add avdd-supply (required) and ldo-in-supply; track ref vs.\n refin supply for REFBUF_EN; set LDO_EN in DEVICE_SETUP when ldo-in\n is present; add software reset fallback via SPI_CONFIG_A register\n- driver: merge ACC_MASK1_REG / ACC_MASK2_REG into ACC_MASK_REG with\n a single ADDR_DESCENDING 16-bit SPI write\n- driver: remove clocks usage; set PWM rate directly without ref clock\n- driver: rename chip info structs (ad4691_chip_info etc.); rename\n *chip → *info in state struct; replace adc_mode enum with manual_mode\n bool; replace ktime sampling_period with u32 cnv_period_ns\n- driver: move IIO_CHAN_INFO_SAMP_FREQ to info_mask_separate with an\n available list for the internal oscillator frequency\n- driver: use regcache MAPLE instead of RBTREE\n- triggered buffer: derive DATA_READY GP pin from interrupt-names in\n firmware (\"gp0\"..\"gp3\") instead of assuming GP0\n- triggered buffer: use regmap_update_bits for DEVICE_SETUP mode toggle\n to avoid clobbering LDO_EN when toggling MANUAL_MODE bit\n- triggered buffer: split buffer setup ops into separate Manual and\n CNV Burst variants (mirrors offload path structure)\n- SPI offload: promote channel storagebits from 16 to 32 to match DMA\n word size; introduce ad4691_manual_channels[] with shift=16 (data in\n upper 16 bits of the 32-bit word); update triggered-buffer paths to\n the same layout for consistency\n- SPI offload: derive GP pin from trigger-source args[0] instead of\n hardcoding GP0; split offload buffer setup ops per mode\n- replace put_unaligned_be32() + FIELD_PREP() with cpu_to_be32() and\n plain bit-shift ops for SPI offload message construction\n- multiple reviewer-requested code style and correctness fixes\n (Andy Shevchenko, Nuno Sá, Uwe Kleine-König, David Lechner)\n- Link to v3: https://lore.kernel.org/r/20260313-ad4692-multichannel-sar-adc-driver-v3-0-b4d14d81a181@analog.com\n\nChanges in v3:\n- Replace GPIO reset handling with reset controller framework\n- Replace two regmap_write() calls for ACC_MASK1/ACC_MASK2 with regmap_bulk_write()\n- Move conv_us declaration closer to its first use\n- Derive spi_device/dev from regmap instead of storing st->spi\n- ad4691_trigger_handler(): use guard(mutex)() and iio_for_each_active_channel()\n- ad4691_setup_triggered_buffer(): return -ENOMEM/-ENOENT directly instead of\n wrapping in dev_err_probe(); fix fwnode_irq_get() check (irq <= 0 → irq < 0)\n- Add GENMASK defines for SPI offload 32-bit message layout; replace manual\n bit-shifts with put_unaligned_be32() + FIELD_PREP()\n- Use DIV_ROUND_CLOSEST_ULL() instead of div64_u64()\n- ad4691_set_sampling_freq(): fix indentation; drop unnecessary else after return\n- ad4691_probe(): use PTR_ERR_OR_ZERO() for devm_spi_offload_get()\n- Link to v2: https://lore.kernel.org/r/20260310-ad4692-multichannel-sar-adc-driver-v2-0-d9bb8aeb5e17@analog.com\n\nChanges in v2:\n- Drop adi,spi-mode DT property; operating mode now auto-detected\n from pwms presence (CNV Clock Mode if present, Manual Mode if not)\n- Reduce from 5 operating modes to 2 (CNV Clock Mode, Manual Mode);\n Autonomous, SPI Burst and CNV Burst modes removed as user-selectable\n modes; Autonomous Mode is now the internal idle/single-shot state\n- Single-shot read_raw always uses internal oscillator (Autonomous\n Mode), independent of the configured buffer mode\n- Replace bulk regulator API with devm_regulator_get_enable() and\n devm_regulator_get_enable_read_voltage()\n- Use guard(mutex) and IIO_DEV_ACQUIRE_DIRECT_MODE scoped helpers\n- Replace enum + indexed chip_info array with named chip_info structs\n- Remove product_id field and hardware ID check from probe\n- Factor IIO_CHAN_INFO_RAW body into ad4691_single_shot_read() helper\n- Use fwnode_irq_get(dev_fwnode(dev), 0); drop interrupt-names from\n DT binding\n- Use devm_clk_get_enabled(dev, NULL); drop clock-names from DT\n binding\n- Use spi_write_then_read() for DMA-safe register writes\n- Use put_unaligned_be16() for SPI header construction\n- fsleep() instead of usleep_range() in single-shot path\n- storagebits 24->32 for manual-mode channels (uniform DMA layout)\n- Collect full scan into vals[16], single iio_push_to_buffers_with_ts()\n- Use pf->timestamp instead of iio_get_time_ns() in trigger handler\n- Remove IRQF_TRIGGER_FALLING (comes from firmware/DT)\n- Fix offload xfer array size ([17]: N channels + 1 state reset)\n- Drop third DT binding example per reviewer request\n- Link to v1: https://lore.kernel.org/r/20260305-ad4692-multichannel-sar-adc-driver-v1-0-336229a8dcc7@analog.com\n\n---\nRadu Sabau (4):\n dt-bindings: iio: adc: add AD4691 family\n iio: adc: ad4691: add initial driver for AD4691 family\n iio: adc: ad4691: add triggered buffer support\n iio: adc: ad4691: add SPI offload support\n\n .../devicetree/bindings/iio/adc/adi,ad4691.yaml | 162 ++\n Documentation/iio/ad4691.rst | 259 +++\n Documentation/iio/index.rst | 1 +\n MAINTAINERS | 9 +\n drivers/iio/adc/Kconfig | 14 +\n drivers/iio/adc/Makefile | 1 +\n drivers/iio/adc/ad4691.c | 1704 ++++++++++++++++++++\n 7 files changed, 2150 insertions(+)\n---\nbase-commit: 11439c4635edd669ae435eec308f4ab8a0804808\nchange-id: 20260302-ad4692-multichannel-sar-adc-driver-78e4d44d24b2\n\nBest regards," }