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{ "id": 2216658, "url": "http://patchwork.ozlabs.org/api/covers/2216658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260327025228.474257-1-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327025228.474257-1-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-03-27T02:52:22", "name": "[0/5] intel_iommu: Enable PRQ support for passthrough device", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260327025228.474257-1-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 497680, "url": "http://patchwork.ozlabs.org/api/series/497680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497680", "date": "2026-03-27T02:52:22", "name": "intel_iommu: Enable PRQ support for passthrough device", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2216658/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=e1857Ll/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=\"75719867\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"75719867\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"221874373\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[PATCH 0/5] intel_iommu: Enable PRQ support for passthrough device", "Date": "Thu, 26 Mar 2026 22:52:22 -0400", "Message-ID": "<20260327025228.474257-1-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=192.198.163.14;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Hi,\n\nWhen svm=on,pasid=N,x-flst=on is configured for virtual vtd, we enable\nguest's support for vSVM. In this case, the host VTD may generate\nrecoverable first stage page fault event, QEMU read the event and inject\nit to guest.\n\nAfter guest handles the event, it sends a page group response, QEMU gets\nthe response and pass it to host VTD.\n\nThis series adds QEMU support for receiving such host events through the\nFAULTQ interface and propagating them to the guest, then catching guest's\nresponses and propagating them to host.\n\nThis patchset depends on pasid support:\nhttps://lore.kernel.org/qemu-devel/20260326091130.321483-1-zhenzhong.duan@intel.com/#t\n\nGIT branch: https://github.com/yiliu1765/qemu/tree/zhenzhong/iommufd_prq\n\nTests:\nTested with DSA wq attached to an user APP which triggers IO page fault on\nprocess page table durging DMA.\n\nThanks\nZhenzhong\n\n\nZhenzhong Duan (5):\n backends/iommufd: Introduce iommufd_backend_alloc_faultq\n backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id\n intel_iommu_accel: Add PRQ injection for passthrough device\n intel_iommu_accel: Accept PRQ response for passthrough device\n intel_iommu_accel: teardown FAULTQ resources in bottom half\n\n hw/i386/intel_iommu_accel.h | 16 +++\n include/hw/i386/intel_iommu.h | 6 +\n include/system/iommufd.h | 7 +-\n backends/iommufd.c | 34 ++++-\n hw/arm/smmuv3-accel.c | 6 +-\n hw/i386/intel_iommu.c | 4 +\n hw/i386/intel_iommu_accel.c | 243 +++++++++++++++++++++++++++++++++-\n hw/vfio/iommufd.c | 2 +-\n backends/trace-events | 3 +-\n hw/i386/trace-events | 2 +\n 10 files changed, 308 insertions(+), 15 deletions(-)" }