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{ "id": 2216518, "url": "http://patchwork.ozlabs.org/api/covers/2216518/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/cover/20260326162832.3135857-1-grzegorz.nitka@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326162832.3135857-1-grzegorz.nitka@intel.com>", "list_archive_url": null, "date": "2026-03-26T16:28:24", "name": "[v4,net-next,0/8] dpll/ice: Add TXC DPLL type and full TX reference clock control for E825", "submitter": { "id": 82711, "url": "http://patchwork.ozlabs.org/api/people/82711/?format=api", "name": "Nitka, Grzegorz", "email": "grzegorz.nitka@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/cover/20260326162832.3135857-1-grzegorz.nitka@intel.com/mbox/", "series": [ { "id": 497620, "url": "http://patchwork.ozlabs.org/api/series/497620/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=497620", "date": "2026-03-26T16:28:24", "name": "dpll/ice: Add TXC DPLL type and full TX reference clock control for E825", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497620/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2216518/comments/", "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=q72k7TrY;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::138; 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envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=<UNKNOWN> ", "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 smtp1.osuosl.org B996F811FA", "OpenDKIM Filter v2.11.0 smtp3.osuosl.org 4D2986084C" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=osuosl.org;\n\ts=default; t=1774542741;\n\tbh=by5z3A0rPanwhNCA2ttCc8M6NhdqITe5QGfzKcZ38Sg=;\n\th=From:To:Date:Subject:List-Id:List-Unsubscribe:List-Archive:\n\t List-Post:List-Help:List-Subscribe:Cc:From;\n\tb=q72k7TrYhORpYuSj12/n4wTQAok/lbvVVbt+tscUbVy0pKnSo7bHE7Pf3Qqe6vYx+\n\t ze91mN+VdoVnQiA3l1YNZEc0nzOc9JHF461uzSfcFB3Oil1MXg0I0sK3IN/uDCKP9q\n\t SUNbLtxrMcEfKejfjouK77vzWGWRJraJSXrnxLdD0ewFbBuYDcN7+VaKQxFa6VZbHP\n\t IqAHrED2FdZzT0Sn9/Ylx0X0JvFEAJxI5Xaa8o6SQY2Z1uRjsHOa2xZb/712btZPlB\n\t XBlF9ANdgdwcKfRBx/BXncX8OJU0RYXPjjE8okDjK41yidebKpjPi1euUMYb2symeu\n\t w5BW9u7qVo65w==", "Received-SPF": "Pass (mailfrom) identity=mailfrom; client-ip=192.198.163.19;\n helo=mgamail.intel.com; envelope-from=grzegorz.nitka@intel.com;\n receiver=<UNKNOWN>", "DMARC-Filter": "OpenDMARC Filter v1.4.2 smtp3.osuosl.org 4D2986084C", "X-CSE-ConnectionGUID": [ "wWGahFFRTW2ggWksyezXkQ==", "yWty21wOQLieRFpmZS22Eg==" ], "X-CSE-MsgGUID": [ "Afj6UhWzQvmnjxEcOUR+ZA==", "2/jK9f1iQ2WB6beh716Fgw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11741\"; a=\"74636524\"", "E=Sophos;i=\"6.23,142,1770624000\"; d=\"scan'208\";a=\"74636524\"", "E=Sophos;i=\"6.23,142,1770624000\"; d=\"scan'208\";a=\"225310843\"" ], "X-ExtLoop1": "1", "From": "Grzegorz Nitka <grzegorz.nitka@intel.com>", "To": "netdev@vger.kernel.org", "Date": "Thu, 26 Mar 2026 17:28:24 +0100", "Message-Id": "<20260326162832.3135857-1-grzegorz.nitka@intel.com>", "X-Mailer": "git-send-email 2.39.3", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774542738; x=1806078738;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=wwTIrqtwLgvHf+RVkDregSmCC7vSro8vZJLp94r7apQ=;\n b=FbGO5AFvyCEZiW9QkxXutjadamopzygC1RXRmbrm3iUTa/tQKNjSwcwx\n FVmlvY8gttZRJ6a7L8f53XmBiWlcdMNilG9FdzTRMTo7aF6mRX93Hv9Xu\n k6BNHgzlIjCMd0uG2StSyJcri+FxlWGTqsl9IrRm6EYyiHtRLxg5KJ2EL\n 4hvSHxafI7XPTPJjjGeg65YFSI0lFpRGCM0GiCeeYDoaXgu+CJi7qKzHP\n GU7KfEQaW4KhUoiwnONfnw8mmXdh3hgoRNmgiZB5dhddfAijR9TJ0mktL\n 0WHsZyT8v7kOlfokS0zsBIFbeWGYRkoNJDZuZ0ZkQqWOy97oRP5yIaPmL\n g==;", "X-Mailman-Original-Authentication-Results": [ "smtp3.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com", "smtp3.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=FbGO5AFv" ], "Subject": "[Intel-wired-lan] [PATCH v4 net-next 0/8] dpll/ice: Add TXC DPLL\n type and full TX reference clock control for E825", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "ivecera@redhat.com, vadim.fedorenko@linux.dev, kuba@kernel.org,\n jiri@resnulli.us, edumazet@google.com, przemyslaw.kitszel@intel.com,\n richardcochran@gmail.com, donald.hunter@gmail.com,\n linux-kernel@vger.kernel.org, arkadiusz.kubalewski@intel.com,\n andrew+netdev@lunn.ch, intel-wired-lan@lists.osuosl.org, horms@kernel.org,\n Prathosh.Satish@microchip.com, anthony.l.nguyen@intel.com, pabeni@redhat.com,\n davem@davemloft.net", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "NOTE: This series is intentionally submitted on net-next (not\nintel-wired-lan) as early feedback of DPLL subsystem changes is\nwelcomed. In the past possible approaches were discussed in [1].\n\nThis series extends the DPLL subsystem and the ICE driver to fully\nsupport transmit‑clock (TXC) reference selection on Intel E825‑class\nhardware. These devices expose a dedicated TX reference clock domain\nseparate from PPS and SyncE/EEC, and they allow switching between\nmultiple PHY‑sourced references (TXC0, EREF0, SyncE). Until now\nthe kernel lacked a DPLL type to represent TXC‑class devices, and\nthe ICE driver had no way to control or report the active TX reference.\nThe series introduces: \n\nSubsystem‑wide improvements:\n\n- A new DPLL type (DPLL_TYPE_TXC) to represent devices that generate a TX\nSERDES reference clock.\n- Improvements to pin registration for fwnode‑identified pins.\n- Addition of a notification source identifier (src_id) for more accurate\npin event routing in both netlink and internal notifiers.\n\nHardware/driver support:\n\n- ZL3073x: allow control of the SyncE_Ref pin state.\n- ICE/E825: full TXC DPLL instance with dedicated pins (EXT_EREF0 and\nSyncE) and proper integration into the notifier/mux logic.\n-A new CPI (Converged PHY Interface) subsystem implementing the low‑level\ncommand protocol required by E825 PHY clocking control.\n- Extension of the Restart AN AQ command with a TX reference clock\nselector.\n- Complete support for selecting, enabling, disabling, and tracking the\nactive TX reference clock for E825 devices, including peer‑PHY routing\nand safe clean‑up of unused clock sources.\n\nThis enables proper userspace‑driven clock control via the DPLL API and\nis a prerequisite for advanced SyncE deployments, link recovery modes, and\nmulti‑clock orchestration on E825 NICs.\n\nPatch summary:\n\ndpll: add new DPLL type for transmit clock (TXC) usage\nIntroduces DPLL_TYPE_TXC and publishes it through netlink.\n\ndpll: allow registering FW‑identified pin with a different DPLL\nRelax the (module, clock_id) matching rules when fwnode pins are\ninvolved.\n\ndpll: extend pin notifier and netlink events with notification source ID\nAdds src_id to pin notification paths and updates all callers.\n\ndpll: zl3073x: allow SyncE_Ref pin state change\nAdvertise hardware support for state toggling.\n\nice: add TX clock (TXC) DPLL interface for E825 devices\nIntroduces the ICE TXC DPLL, its pins, and relations to existing PHY\nfwnode pins.\n\nice: implement CPI support for E825C\nAdds the CPI command engine used for PHY‑side clock control.\n\nice: add Tx reference clock index handling to AN restart command\nWires the refclk field into the AQ Restart AN command.\n\nice: add TX reference clock (tx_clk) control for E825 devices\nImplements full clock‑selection logic, state tracking, cleanup, and\nDPLL pin ops integration.\n\n\nTesting was performed on E825C hardware in multi‑port configurations,\nverifying TXC pin exposure, SyncE/EREF0 switching via DPLL netlink, and\nlink recovery across all combinations.\n\n[1] https://lore.kernel.org/netdev/20250905160333.715c34ac@kernel.org/\n\nChanges in v4:\n - rebased\n - edited, shortened the commit message in 3/8 patch\n - moved ice_get_ctrl_pf to the header file (patch 8/8) and\n removed duplicated static definitions from ice_ptp and ice_txlck\n modules\n - add NULL/invalid pointer checker for returned pointer from\n ice_get_ctrl_pf (patch 8/8)\n - edited error message in case AN restart failure (patch 8/8)\n\nChanges in v3:\n- improved commit message (patch 1/8, AI review comment)\n- improved deinitialization path in ice_dpll_deinit_txclk_pins to\n avoid potential NULL dereference. NULL checking moved to\n ice_dpll_unregister_pins (patch 5/8, found by AI review)\n- removed redundant semicolon (patch 6/8)\n\nChanges in v2:\n- rebased\n- added autogenerated DPLL files (patch 1/8)\n- fixed checkpatch 'parenthesis alignment' warning (patch 2/8)\n- fixed error path in ice_dpll_init_txclk_pins (AI warning, patch 5/8)\n- fixed kdoc warnings (patch 6/8, patch 8/8)\n\nGrzegorz Nitka (8):\n dpll: add new DPLL type for transmit clock (TXC) usage\n dpll: allow registering FW-identified pin with a different DPLL\n dpll: extend pin notifier and netlink events with notification source\n ID\n dpll: zl3073x: allow SyncE_Ref pin state change\n ice: add TX clock (TXC) DPLL interface for E825 devices\n ice: implement CPI support for E825C\n ice: add Tx reference clock index handling to AN restart command\n ice: add TX reference clock (tx_clk) control for E825 devices\n\n Documentation/netlink/specs/dpll.yaml | 3 +\n drivers/dpll/dpll_core.c | 32 +-\n drivers/dpll/dpll_core.h | 2 +-\n drivers/dpll/dpll_netlink.c | 10 +-\n drivers/dpll/dpll_netlink.h | 4 +-\n drivers/dpll/dpll_nl.c | 2 +-\n drivers/dpll/zl3073x/prop.c | 9 +\n drivers/net/ethernet/intel/ice/Makefile | 2 +-\n drivers/net/ethernet/intel/ice/ice.h | 12 +\n .../net/ethernet/intel/ice/ice_adminq_cmd.h | 2 +\n drivers/net/ethernet/intel/ice/ice_common.c | 5 +-\n drivers/net/ethernet/intel/ice/ice_common.h | 2 +-\n drivers/net/ethernet/intel/ice/ice_cpi.c | 347 ++++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_cpi.h | 69 ++++\n drivers/net/ethernet/intel/ice/ice_dpll.c | 327 +++++++++++++++--\n drivers/net/ethernet/intel/ice/ice_dpll.h | 6 +\n drivers/net/ethernet/intel/ice/ice_lib.c | 3 +-\n drivers/net/ethernet/intel/ice/ice_ptp.c | 27 +-\n drivers/net/ethernet/intel/ice/ice_ptp.h | 7 +\n drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 37 ++\n drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 34 ++\n drivers/net/ethernet/intel/ice/ice_sbq_cmd.h | 5 +-\n drivers/net/ethernet/intel/ice/ice_txclk.c | 256 +++++++++++++\n drivers/net/ethernet/intel/ice/ice_txclk.h | 41 +++\n include/linux/dpll.h | 1 +\n include/uapi/linux/dpll.h | 2 +\n 26 files changed, 1194 insertions(+), 53 deletions(-)\n create mode 100644 drivers/net/ethernet/intel/ice/ice_cpi.c\n create mode 100644 drivers/net/ethernet/intel/ice/ice_cpi.h\n create mode 100644 drivers/net/ethernet/intel/ice/ice_txclk.c\n create mode 100644 drivers/net/ethernet/intel/ice/ice_txclk.h\n\n\nbase-commit: d1e59a46973719e458bec78d00dd767d7a7ba71f" }