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{ "id": 2216366, "url": "http://patchwork.ozlabs.org/api/covers/2216366/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260326110948.68908-1-akhilrajeev@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326110948.68908-1-akhilrajeev@nvidia.com>", "list_archive_url": null, "date": "2026-03-26T11:09:37", "name": "[v4,00/10] Add GPCDMA support in Tegra264", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260326110948.68908-1-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 497568, "url": "http://patchwork.ozlabs.org/api/series/497568/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497568", "date": "2026-03-26T11:09:37", "name": "Add GPCDMA support in Tegra264", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497568/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2216366/comments/", "headers": { "Return-Path": "\n <linux-tegra+bounces-13283-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=BbF7JyGb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; 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pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>, Rob Herring\n\t<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley\n\t<conor+dt@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, \"Jonathan\n Hunter\" <jonathanh@nvidia.com>, Laxman Dewangan <ldewangan@nvidia.com>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>, <dmaengine@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "Akhil R <akhilrajeev@nvidia.com>", "Subject": "[PATCH v4 00/10] Add GPCDMA support in Tegra264", "Date": "Thu, 26 Mar 2026 16:39:37 +0530", "Message-ID": "<20260326110948.68908-1-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PEPF00003448:EE_|DS2PR12MB9613:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d61deabd-a703-498b-464a-08de8b283d8b", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|1800799024|36860700016|7416014|376014|921020|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tR9huB1jJKR/zGR5FECnBaEM6fsSdbAtVo6pP23IMvnWvMhEr8NYuTewxLpQ8iqsaGEMjguQ4lsVN79HeOE9vxKs+pcuHu1AhCT0G3W705zhPu+MQYfv7bixXaAuZdgzWKwOmPLIQ8fakxv38lT2qN82je0bj76aYoo/9UuuWjpQeZZyxl51JlAVA7Plfmf4BCAwL9luYeI3iJdaivBi5919HeURXhBCcjVwMEKWZSDQ/AbNfTS+lEQ9hiR2hFQNn8GWba28KlvFXVCnStZlmAR5GRS235NvfPrLGmfBFOkMZIqAgV7ZysbGkGkCN0RVmWCgu/iBC7AelxY0jigCysRMXx+pC+B45HExAefyQXQoyGA8fFQKAOEI7UpsHmXB1hjEMEpZDqyXjYCbpEWPOTFEbnJswGuGcCLCaEqj1uf0rnYtyckPGF6StBKUxSuFoAeha52CF8orPN1hgCKcNl2Iq9C8adGIX6fGbJzYSs9aIm934iM2JsvZ7EX0hcELHklB74tf0Vw3TipNKCvyRGezCcZeNzcib1y8//vzUApizqhHFKlgtESzqEk+SNsdBKda9N0yG7dWb3WnjBDo9/VyLD3CgBcmsmN8vaFEfhO3tLZzc4NkMwqhC2EYi9XA4XHxkMUaYGMr/Y0R+m7xQ0kxllBUDHtYvxbylzei5AFOjEFPMjSguNfUBh0+WAi/3fxcey+A69yGkVwfN0jBEPlA8nnGAnnmr61DULMka0JykJeO/kYooPe3GFDG3z4+9r+eViEG2xKwbKg8vakuZtD/ZMqep2tII6vjNnPwFfO65Hm/dVPm0ePTPqDUU9EUQ", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(7416014)(376014)(921020)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tpsLWIj6jD/vKpmc7CqATCPc8TbjosmPMBebm5/KukdZPeglQ3JNrllAL8+uoxVD7HCoFuIrI0NGU5vFrtu83jaS5ovHBmnAwPZWpoKusRL2sX92jQshRsIm71DeRhJo6eqRs0CANClz29Hu2QllSOquWyWys+x6J1HEY0pnGxFIS7OGkO+s5FHPtZPkCTyhVm5C/C+0aaNLDeQOOs7BTrI4CtL7p3uWB0DYXSdMGWgcC9r0YKJDwtbkkjVFeMRsTtlpfWIe/uyAdCeIeprU5kTi0LeHY++MWE1eL+tzZnsJxVRSvp4CyhQQFIZG5dSjdAZHZSyNJqlg3ZhENLGt/JTeyG6TMP6xMSpIhRXQQc8IAoJtKGePNPJPzjg6HiX+/Gxu/cTpvYQE1GZlRROhk52QSrQe7GrkxdQlOZKjIx/TU1+QIUV1QdzQT+TEJB9Jm", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "26 Mar 2026 11:10:07.9195\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d61deabd-a703-498b-464a-08de8b283d8b", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDS2PEPF00003448.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS2PR12MB9613" }, "content": "This series adds support for GPCDMA in Tegra264 with additional\nsupport for separate stream ID for each channel. Tegra264 GPCDMA\ncontroller has changes in the register offsets and uses 41-bit\naddressing for memory. Add changes in the tegra186-gpc-dma driver\nto support these.\n\nv3->v4:\n- Split device tree changes to two patches.\n- Reordered patches to have fixes first.\n- Added fixes tag to dt-bindings and device tree changes.\nv2->v3:\n- Add description for iommu-map property and update commit descriptions.\n- Use enum for compatible string instead of const.\n- Remove unused registers from struct tegra_dma_channel_regs.\n- Use devm_of_dma_controller_register() to register the DMA controller.\n- Remove return value check for mask setting in the driver as the bitmask\n value is always greater than 32.\nv1->v2:\n- Fix dt_bindings_check warnings\n- Drop fallback compatible \"nvidia,tegra186-gpcdma\" from Tegra264 DT\n- Use dma_addr_t for sg_req src/dst fields and drop separate high_add\n variable and check for the addr_bits only when programming the\n registers.\n- Update address width to 39 bits for Tegra234 and before since the SMMU\n supports only up to 39 bits till Tegra234.\n- Add a patch to do managed DMA controller registration.\n- Describe the second iteration in the probe.\n- Update commit descriptions.\n\nAkhil R (10):\n dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional\n arm64: tegra: Remove fallback compatible for GPCDMA\n dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property\n dmaengine: tegra: Make reset control optional\n dmaengine: tegra: Use struct for register offsets\n dmaengine: tegra: Support address width > 39 bits\n dmaengine: tegra: Use managed DMA controller registration\n dmaengine: tegra: Use iommu-map for stream ID\n dmaengine: tegra: Add Tegra264 support\n arm64: tegra: Enable GPCDMA in Tegra264 and add iommu-map\n\n .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 34 +-\n .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 4 +\n arch/arm64/boot/dts/nvidia/tegra264.dtsi | 3 +-\n drivers/dma/tegra186-gpc-dma.c | 435 +++++++++++-------\n 4 files changed, 292 insertions(+), 184 deletions(-)" }