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{ "id": 2216285, "url": "http://patchwork.ozlabs.org/api/covers/2216285/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260326091130.321483-1-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326091130.321483-1-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-03-26T09:11:14", "name": "[v2,00/14] intel_iommu: Enable PASID support for passthrough device", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260326091130.321483-1-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 497556, "url": "http://patchwork.ozlabs.org/api/series/497556/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497556", "date": "2026-03-26T09:11:19", "name": "intel_iommu: Enable PASID support for passthrough device", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497556/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2216285/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=TmS3Cq4e;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 26 Mar 2026 05:11:52 -0400", "from fmviesa001.fm.intel.com ([10.60.135.141])\n by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 02:11:46 -0700", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 02:11:42 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774516311; x=1806052311;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=gj5e/lV6Na+orv9h9pfSru8Da51T+AkraUGg0qWEX8o=;\n b=TmS3Cq4ey71OO7h97AGbLvKVFlGsfJoTwA7VudQQsEKO4bBLBgscXUFP\n hdC9YO1zR99gBzXfOq3ZmVFY33S0wXqMDladeckpAbG5+FrsYMAVgQtnW\n qIxYP9cHJoww2mZGdHRgT6t07CEY88HYhqesbAHCizfmNMaoTKYdPBsW+\n Qiu3HTq172HnkY5XYH7VaiU/D1C1+hnpOZZ0rJqDuQF+FMlqObN08N4x9\n 4b54CjAt0MoOpQhbN0D1SWXfQz04VKq96GONozvVTfbvAesoOG2HIAf+O\n k6cbaFeSI28BDGlqvs/568MANQ8xW8Kx+oISx2AVp3jgYAeORhfxZh+Yx Q==;", "X-CSE-ConnectionGUID": [ "gg88DtZhQBKg22ksU9UbeQ==", "PDeQ5Y0TTlii7JoJjzY2aQ==" ], "X-CSE-MsgGUID": [ "QkX8ZDoFRSC1WNwr+6ez2g==", "tRYd33VgSyC89mW+2BdbPw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11740\"; a=\"75531298\"", "E=Sophos;i=\"6.23,141,1770624000\"; d=\"scan'208\";a=\"75531298\"", "E=Sophos;i=\"6.23,141,1770624000\"; d=\"scan'208\";a=\"248368543\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[PATCH v2 00/14] intel_iommu: Enable PASID support for passthrough\n device", "Date": "Thu, 26 Mar 2026 05:11:14 -0400", "Message-ID": "<20260326091130.321483-1-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=198.175.65.17;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Hi,\n\nNow we already support first stage translation with passthrough device\nbacked by nested translation in host, but only for PASID_0.\n\nStructure VTDAddressSpace includes some elements suitable for emulated\ndevice and passthrough device without PASID, e.g., address space,\ndifferent memory regions, etc, it is also protected by vtd iommu lock,\nall these are useless and become a burden for passthrough device with\nPASID.\n\nWhen there are lots of PASIDs used in one device, the AS and MRs are\nall registered to memory core and impact the whole system performance.\n\nSo instead of using VTDAddressSpace to cache pasid entry for each pasid\nof a passthrough device, we define a light weight structure\nVTDAccelPASIDCacheEntry with only necessary elements for each pasid. We\nwill use this struct as a parameter to conduct binding/unbinding to\nnested hwpt, to record the current binded nested hwpt and even future\nPRQ support. It's also designed to support PASID_0.\n\nThe potential full definition of VTDAccelPASIDCacheEntry may like:\n\n typedef struct VTDAccelPASIDCacheEntry {\n VTDHostIOMMUDevice *vtd_hiod;\n VTDPASIDEntry pasid_entry;\n uint32_t pasid;\n uint32_t fs_hwpt_id;\n uint32_t fault_id;\n int fault_fd;\n QLIST_HEAD(, VTDPRQEntry) vtd_prq_list;\n IOMMUPRINotifier pri_notifier_entry;\n IOMMUPRINotifier *pri_notifier;\n QLIST_ENTRY(VTDAccelPASIDCacheEntry) next;\n } VTDAccelPASIDCacheEntry;\n\nGIT branch: https://github.com/yiliu1765/qemu/tree/zhenzhong/iommufd_pasid\n\nPATCH01-06: Some preparing work\nPATCH07-10: Handle PASID entry addition and removal\nPATCH11-12: Support pasid binding and unbinding\nPATCH13-14: Add PASID related check and enable PASID for passthrough device\n\nThis patchset depends on a kernel feature enhancement[1] to work.\n\nTests:\nTested with DSA device which driver uses 2 PASIDs by default.\n\nThanks\nZhenzhong\n\n[1] https://lore.kernel.org/all/20260205023405.41583-1-zhenzhong.duan@intel.com/\n\nChangelog:\nv2:\n- move the check \"s->pasid > PCI_EXT_CAP_PASID_MAX_WIDTH\" to patch5 (Clement)\n- move #include \"hw/core/iommu.h\" before #include \"hw/core/qdev.h\" (liuyi)\n- polish the comment about @Pasid parameter (Liuyi)\n- s/pe/pasid_entry, s/as_it/hiod_it, s/vtd_find_add_pc/vtd_accel_fill_pc (Liuyi)\n- s/VTDACCELPASIDCacheEntry/VTDAccelPASIDCacheEntry (Liuyi)\n- add explanation in code about PASID removal before addition (Liuyi)\n- polish the comment about scope of VTDAccelPASIDCacheEntry vs VTDPASIDCacheEntry (Liuyi)\n- add an optimization to bypass PASID entry addition for PASID selective pv_inv_dsc (Liuyi)\n\nv1:\n- use naming pattern \"XXX_SET_THENAME\" same as smmu (Clement)\n- fix s->pasid check (Clement)\n\nRFCv2:\n- extend attach/detach_hwpt() instead of introducing new callbacks (Shammer)\n- Define IOMMU_NO_PASID for device attachment without pasid (Nicolin)\n- update vtd_destroy_old_fs_hwpt()'s parameter for naming consistency (Clement)\n- check pasid bits size to be no more than 20 bits (Clement)\n- initialize local variable max_pasid_log2 to 0 (Cédric)\n\n\nZhenzhong Duan (14):\n vfio/iommufd: Extend attach/detach_hwpt callback implementations with\n pasid\n iommufd: Extend attach/detach_hwpt callbacks to support pasid\n vfio/iommufd: Create nesting parent hwpt with IOMMU_HWPT_ALLOC_PASID\n flag\n intel_iommu: Create the nested hwpt with IOMMU_HWPT_ALLOC_PASID flag\n intel_iommu: Change pasid property from bool to uint8\n intel_iommu: Export some functions\n intel_iommu_accel: Handle PASID entry addition for pc_inv_dsc request\n intel_iommu_accel: Handle PASID entry removal for pc_inv_dsc request\n intel_iommu_accel: Bypass PASID entry addition for just deleted entry\n intel_iommu_accel: Handle PASID entry removal for system reset\n intel_iommu_accel: Support pasid binding/unbinding and PIOTLB flushing\n intel_iommu_accel: drop _lock suffix in\n vtd_flush_host_piotlb_all_locked()\n intel_iommu_accel: Add pasid bits size check\n intel_iommu: Expose flag VIOMMU_FLAG_PASID_SUPPORTED when configured\n\n hw/i386/intel_iommu_accel.h | 34 ++-\n hw/i386/intel_iommu_internal.h | 43 +++-\n include/hw/core/iommu.h | 2 +\n include/hw/i386/intel_iommu.h | 4 +-\n include/hw/vfio/vfio-device.h | 1 +\n include/system/iommufd.h | 16 +-\n backends/iommufd.c | 9 +-\n hw/arm/smmuv3-accel.c | 12 +-\n hw/i386/intel_iommu.c | 83 +++----\n hw/i386/intel_iommu_accel.c | 420 +++++++++++++++++++++++++++------\n hw/vfio/device.c | 11 +\n hw/vfio/iommufd.c | 56 +++--\n hw/vfio/trace-events | 4 +-\n 13 files changed, 524 insertions(+), 171 deletions(-)" }