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{ "id": 2216133, "url": "http://patchwork.ozlabs.org/api/covers/2216133/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260325212628.1234082-1-chunn@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325212628.1234082-1-chunn@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T21:26:24", "name": "[0/4] arm64: tegra: add initial Tegra238 and E2426-1099+E2423-1099 support", "submitter": { "id": 92971, "url": "http://patchwork.ozlabs.org/api/people/92971/?format=api", "name": "Chun Ng", "email": "chunn@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260325212628.1234082-1-chunn@nvidia.com/mbox/", "series": [ { "id": 497514, "url": "http://patchwork.ozlabs.org/api/series/497514/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497514", "date": "2026-03-25T21:26:26", "name": "arm64: tegra: add initial Tegra238 and E2426-1099+E2423-1099 support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497514/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2216133/comments/", "headers": { "Return-Path": "\n <linux-tegra+bounces-13255-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=BmTXbIbb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Chun Ng <chunn@nvidia.com>", "To": "<linux-tegra@vger.kernel.org>", "CC": "<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,\n\t<thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <chunn@nvidia.com>,\n\t<ankitag@nvidia.com>", "Subject": "[PATCH 0/4] arm64: tegra: add initial Tegra238 and\n E2426-1099+E2423-1099 support", "Date": "Wed, 25 Mar 2026 21:26:24 +0000", "Message-ID": "<20260325212628.1234082-1-chunn@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CH3PEPF00000015:EE_|SN7PR12MB7882:EE_", "X-MS-Office365-Filtering-Correlation-Id": "8269228c-bf3c-402a-eec4-08de8ab5468d", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|36860700016|1800799024|376014|82310400026|42112799006|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\t8RF0XuT1FYxOocL2apF06M4J+wD42aeyNQr1aWDLxKqrfzn+9CRlEuPWdoINuUdE5kC9WDluMdM4nl5R6wxwpfgeKybdTdzRFS3ooUsxPzQEneG3Gmd3uH2RzYEjQ6OTt9/fC6qXT0OjJR7U8DNG1i4phScjT7piqXTqCpRZxvUSQX3sKG820mUAmGs+mbjupLaFTtJ8IkS73pmezQQ4PGiNkk8A+NbBQw+OqaHHUSzD1YUHy5i0Y/GFTjAP+Mueylg3+00mOTutCQe5k9x4ZMQ//lZzkSreLKbv/t4aTGS6dAZ8jEr9/Y3vToRCWQzanxRuy8rzYwVHJfWQtT1bKg4q4KiMFarDc2e0r7U5y7bwalroUxc/dh4dTW2cnNerYG//kbTaBvvkyU/++JgEU+H12CwSvd/NgGr97AodBbt83gFPW1x+h58hPi0qOfgAFYg0M/z+xvBCPv3cax1SWiImRuz8tNwoD5PR/lWutb0lfWahSQQnjN/FqbwQStmQkcdZUzDcHMVEGpQNDJBtIVmglqIKq/VDk02a9uQ7t2DnFUUHuPgY0qA11k0V02TIbNvEeScJ1yUhxTzAvjXe/aKHUd7eJHibqz2SYtdlojLU7NXwdvg7FVgILiQ/IkkjShTJ7TfB8orE7n4M5vN9O7lU9U9PgPnibN/8P0YOxScJWy7BoP4ez8WLO0fjfjLpf33uljkxXAIOrekhoAIO+/ZVcjCVYQi0b71+cRS68ZHVdqA5pBnqH6O00Uf0V6LttGyNnZrsZLQTpZQqp6Ngpw==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(376014)(82310400026)(42112799006)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tp3xjmFDBhupKR9xO910Ob79lCUuLzxMpFEM9cvrcNzQeJDMIyVcz8uYmBGP3lYI2t4oZVagwsygrPzxaOwS9F6kTe4V3PKIzBBmX9SoYymRT0l/djbs/CA6t3cwt9ARcvf0uAMcG73EagueicB7FoKNpD7ZUkmkcAhErwS8G6QqQ4I0yQpsZp8iimnC0fGPFVlmZmSMzZagqATUPcu0tnXW62oZW9aJcfOplgW3UxegKgUPNNHu22i7Lsu26ZpPp9ic9OP01qcOjLSDYrV2Zw+HJEF8u+ZDt+a3sg4X75Ad62H1j1afV7tqjf0HebkPEgSDW+ero4GzfkAlEf6aFyL2l1HX+oZUj+meuV5jAexR14Td8cu8o5MJ9dsYG/D3XnTaW1mixvyysCTkJvWiyA3pdwPhgd8e+oWRTjgPcmYHe/4clsd+FXWxHLRaVUdGQ", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2026 21:27:10.8922\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8269228c-bf3c-402a-eec4-08de8ab5468d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCH3PEPF00000015.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SN7PR12MB7882" }, "content": "Hi all,\n\nThis series adds initial support for the NVIDIA Tegra238 SoC and the\nE2426-1099+E2423-1099 engineering reference platform. The series follows\nthe pattern used for Tegra234 and other recent Tegra SoCs.\n\nIt introduces Tegra238 clock and reset binding headers, documents the\nE2426-1099+E2423-1099 platform compatibles, relaxes the tegra186-hsp\nbinding schema for HSP configurations used on Tegra238, and adds the\ninitial Tegra238 SoC device tree plus board DTS.\n\nThe device tree added here is minimal scaffolding only. It is not yet\nbootable, and further enablement will follow in later series.\n\nThe patch order puts bindings before implementation: clock/reset IDs\nfirst, then platform documentation, then the HSP schema update required\nby tegra238.dtsi, and finally the SoC and board device trees.\n\nThis series is based on linux-next commit 785f0eb2f85d\n(\"Add linux-next specific files for 20260320\").\n\nTested with:\n- make ARCH=arm64 CHECK_DTBS=yes nvidia/tegra238-e2426-1099+e2423-1099.dtb\n- make ARCH=arm64 dt_binding_check\n\nChun Ng (4):\n dt-bindings: tegra: Add Tegra238 clock and reset definitions\n dt-bindings: tegra: Document E2426-1099+E2423-1099 platform\n dt-bindings: mailbox: tegra186-hsp: allow doorbell+shared or\n shared-only\n arm64: tegra: add e2426-1099+e2423-1099 support\n\n .../devicetree/bindings/arm/tegra.yaml | 4 +\n .../bindings/mailbox/nvidia,tegra186-hsp.yaml | 7 +\n arch/arm64/boot/dts/nvidia/Makefile | 2 +\n .../nvidia/tegra238-e2426-1099+e2423-1099.dts | 16 +\n arch/arm64/boot/dts/nvidia/tegra238.dtsi | 190 ++++++++++++\n include/dt-bindings/clock/nvidia,tegra238.h | 279 ++++++++++++++++++\n include/dt-bindings/reset/nvidia,tegra238.h | 125 ++++++++\n 7 files changed, 623 insertions(+)\n create mode 100644 arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts\n create mode 100644 arch/arm64/boot/dts/nvidia/tegra238.dtsi\n create mode 100644 include/dt-bindings/clock/nvidia,tegra238.h\n create mode 100644 include/dt-bindings/reset/nvidia,tegra238.h\n\n\nbase-commit: 785f0eb2f85decbe7c1ef9ae922931f0194ffc2e" }