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{ "id": 2215775, "url": "http://patchwork.ozlabs.org/api/covers/2215775/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260325-t264-pwm-v2-0-998d885984b3@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325-t264-pwm-v2-0-998d885984b3@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T10:16:58", "name": "[v2,0/7] Tegra264 PWM support", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260325-t264-pwm-v2-0-998d885984b3@nvidia.com/mbox/", "series": [ { "id": 497411, "url": "http://patchwork.ozlabs.org/api/series/497411/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497411", "date": "2026-03-25T10:16:58", "name": "Tegra264 PWM support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497411/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2215775/comments/", "headers": { "Return-Path": "\n <linux-tegra+bounces-13198-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=kbXHBaTe;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=XYx6BcI5f/wraCUYhJFxHx31QYEkcLZCOZ2VSLWdCko=;\n b=kbXHBaTeMtBg6o7zrXxLlGpI3MlKOmGHnSlA4PaPGpXPM3UcD1GnD4RvUw2S2XZAjR102z0pzB9Fzux/Webk66Y/aY8yqP+/yTfmH7pJHKZzdveJ8xl84HDkekmauBC2/VnhMk6CtiYN3xW9mhQxDAvX5VouDeGWGFT912BDIwLvFDfUDrCFq4QbrzNnXnrTDNGgL3M5x2RVrTlpoyw6kBferum0wohSlCoR+S3EVh6FN4q8Ivp9g8mneFqlNLXkaBXzBH+AJooCJ4jseE6v6rSgK5B+fzDlnkLJmIjJ5cO9cOMPNIogKKpi18LydE+Z7p2lGYvjA4exFKvotWuM9Q==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Subject": "[PATCH v2 0/7] Tegra264 PWM support", "Date": "Wed, 25 Mar 2026 19:16:58 +0900", "Message-Id": "<20260325-t264-pwm-v2-0-998d885984b3@nvidia.com>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "X-B4-Tracking": "v=1; b=H4sIAAAAAAAC/03Myw6CMBCF4Vchs3bM9AJEV76HYUF6kVlQSEuqh\n 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"X-MS-Exchange-AntiSpam-MessageData-1": "WvB/HqxbIEloIw==", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d00a3ae6-e1f3-4d8f-449d-08de8a57ba28", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2026 10:17:32.4558\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n NAKXQOxlnNvIT/5qOEy9wnT2KdxlLHo4la29U3t8SJHcl54c7LXxrqYbs/odX+Y7qJaszPLuj+hndt0as6IT8Q==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS5PPFA3734E4BA" }, "content": "Hello,\n\nthis adds support for the PWM controller on Tegra264. The controller\nis similar to previous generations, but the register fields are\nwidened, the depth is made configurable, and the enable bit moves\nto a different spot.\n\nThis series adds only basic support with fixed depth -- configurable\ndepth will come later.\n\nPatch 1 adds device tree bindings for the Tegra194 and Tegra264\ncompatible strings.\n\nPatches 2 to 6 contain the PWM driver changes.\n\nPatch 7 adds device tree nodes for the PWM controllers on Tegra264.\n\nThanks,\nMikko\n\n---\nChanges in v2:\n- Added device tree binding and Tegra264 device tree patches by Thierry.\n- Link to v1: https://lore.kernel.org/r/20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com\n\n---\nMikko Perttunen (4):\n pwm: tegra: Modify read/write accessors for multi-register channel\n pwm: tegra: Parametrize enable register offset\n pwm: tegra: Parametrize duty and scale field widths\n pwm: tegra: Add support for Tegra264\n\nThierry Reding (2):\n dt-bindings: pwm: Document Tegra194 and Tegra264 controllers\n arm64: tegra: Add PWM controllers on Tegra264\n\nYi-Wei Wang (1):\n pwm: tegra: Avoid hard-coded max clock frequency\n\n .../bindings/pwm/nvidia,tegra20-pwm.yaml | 2 +\n arch/arm64/boot/dts/nvidia/tegra264.dtsi | 72 +++++++++++\n drivers/pwm/pwm-tegra.c | 141 ++++++++++++++-------\n 3 files changed, 172 insertions(+), 43 deletions(-)\n---\nbase-commit: 11439c4635edd669ae435eec308f4ab8a0804808\nchange-id: 20260303-t264-pwm-57e10d039df1" }