Cover Letter Detail
Show a cover letter.
GET /api/covers/2215701/?format=api
{ "id": 2215701, "url": "http://patchwork.ozlabs.org/api/covers/2215701/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260325050011.66722-1-jay.chang@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325050011.66722-1-jay.chang@sifive.com>", "list_archive_url": null, "date": "2026-03-25T05:00:09", "name": "[v2,0/2] Bug fixes and IPSR.PMIP support", "submitter": { "id": 90508, "url": "http://patchwork.ozlabs.org/api/people/90508/?format=api", "name": "Jay Chang", "email": "jay.chang@sifive.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260325050011.66722-1-jay.chang@sifive.com/mbox/", "series": [ { "id": 497382, "url": "http://patchwork.ozlabs.org/api/series/497382/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497382", "date": "2026-03-25T05:00:10", "name": "Bug fixes and IPSR.PMIP support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497382/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2215701/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=IuBGKRbB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgZVq2GLZz1xy3\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 16:01:07 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w5GM4-0005b1-IL; Wed, 25 Mar 2026 01:00:32 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <jay.chang@sifive.com>)\n id 1w5GLy-0005Ww-HF\n for qemu-devel@nongnu.org; Wed, 25 Mar 2026 01:00:26 -0400", "from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <jay.chang@sifive.com>)\n id 1w5GLw-00078L-Bv\n for qemu-devel@nongnu.org; Wed, 25 Mar 2026 01:00:26 -0400", "by mail-pj1-x1029.google.com with SMTP id\n 98e67ed59e1d1-35a288a2c00so917274a91.2\n for <qemu-devel@nongnu.org>; Tue, 24 Mar 2026 22:00:23 -0700 (PDT)", "from jchang-1875.internal.sifive.com ([136.226.240.163])\n by smtp.gmail.com with ESMTPSA id\n 98e67ed59e1d1-35c03149db2sm4218866a91.9.2026.03.24.22.00.15\n (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256);\n Tue, 24 Mar 2026 22:00:17 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=sifive.com; s=google; t=1774414823; x=1775019623; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:from:to:cc:subject:date:message-id:reply-to;\n bh=2Dnt+PDDAZp/+TV963oEFZh4GPDRIAX7fgbJmYYOAko=;\n b=IuBGKRbBg8zVrtWJmtKQM+t0o/wZouY90oAOyUO2g+KTRkWIRsKLaciD79cSUf26wo\n nwB61Gn22FCb/gU/QOxVMMYtdOQ+d5rhRhq3dC7t2LlVWeKbIQB4J9fgtcS0flKuZmOe\n VtsWjmy1WCSnX0bUgP3LRds6UD/r+yKkwoa60SUOGA6ZsgsvOGDk/3NKgSkhsgHI78Vk\n UFGNfUrAe9gxItK/8CqZ6krEdIlZ+GOSuEb/Xs4T633WisLskJyTw59JxK0vdThpcyxA\n JmZVic6AfZL2//6ntmr5cDeKdiDE8NzTFkptT3KLTwFlk5MzVyWP02Y7BFC8oga4xMiM\n ceaQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774414823; x=1775019623;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date\n :message-id:reply-to;\n bh=2Dnt+PDDAZp/+TV963oEFZh4GPDRIAX7fgbJmYYOAko=;\n b=oYpjd8+/EE1GezLIkQoCWRRWRhs7P9L2OlSp32PshXCxjzhsJ+UTLw6DV/LtLhArQe\n JQYiZ6BY1u8suDD4xhiZ7bzjQS/mgjXs/A4EvJP3aVArBcoB6RzCJ4TMZ/Ng1cWQ7SDv\n z+6Ud12F6q5mi3Dt7s7ftkNPTPdojU4DDa5jdVQSWjgHHhi7wii4Ge8z7staP7VJZWtg\n P/hdahqpXxWTO3bNkfz0b9qlw0lTyjeI/HP76/onVGGKAd7PySA+xGHT/DhBue73S+hH\n 0fF/5IKknbU3cmjqu1JlllRWFmAKKCYxesmmcw+GgRmCvQcoVRjYXYxaBSLny3qZtokJ\n xHuA==", "X-Gm-Message-State": "AOJu0YzllomEa0QaT7Auu8peWiclv9lKtWWq1184M5+9FKBxUW6AE0ce\n s7eoCdGO2IAolYj4p+hiAqTbqmMGUIP5IL8OK4A0n+BtDCaNitljps3hn5wpdiidTkm9JCbalRv\n fu0qSWM63UOkcug6oySGlOcV9nV6US8DS31VQBegcRo7T/h0SDicgi8m5L6TIa/SQNQ09zJlJmk\n okoZxAyH0cHNvb9zTstS/VdydjNSQ3xtf1kCmkDkb35es=", "X-Gm-Gg": "ATEYQzy+BSxUoRYy18u9hw1sWq1iaEmvqtHXUUanzLiUn+JKnk3a9DAAtwXbxiUbksY\n wkOWva4xlI+uYg9dVuHRN4z3rSzTMeo5RyOKmnjggEuzFnN58TovquHuz1Gkt2crBd9Kh2ThEyU\n hkfHfWteK+dTl/rydOuSQ8+X2sXXD2k/pd3qbKr6Ez7gUTgWBqT+5OeV8nYjBn1L12zYhyayXIy\n eMsS5wuhwkeQYc/tF8/wkkJn5ifiIDY6LvncHdHfSwE3xV2UPkGe4kNAE3Yjb8917rmfJrCtKkC\n 7Sn/Jd55YeCbp0InwsNcxH4Bz9BLIDEJS6KMnglKa+/4KVyRKcRd+ctuEo5+FqvXLZJWn8iZKNW\n ty8dtC9VUA3yIATRiGyqnzYAk9nVKDEp4Cc7l3x+chQ4P44btYtAWxwJccEGJi9wUAh3hZuDcef\n CcOAxsqlIHHmk6mOTg6v9uSIeiBK6XSvSJKzuozBvKubr+4oI6Pe3Q6kWeNJ9dCw==", "X-Received": "by 2002:a17:90b:164c:b0:33b:bed8:891c with SMTP id\n 98e67ed59e1d1-35c0ddc503bmr1804841a91.23.1774414817611;\n Tue, 24 Mar 2026 22:00:17 -0700 (PDT)", "From": "Jay Chang <jay.chang@sifive.com>", "To": "qemu-devel@nongnu.org,\n\tqemu-riscv@nongnu.org", "Cc": "Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>,\n Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>, Jay Chang <jay.chang@sifive.com>", "Subject": "[PATCH v2 0/2] Bug fixes and IPSR.PMIP support ", "Date": "Wed, 25 Mar 2026 13:00:09 +0800", "Message-ID": "<20260325050011.66722-1-jay.chang@sifive.com>", "X-Mailer": "git-send-email 2.48.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::1029;\n envelope-from=jay.chang@sifive.com; helo=mail-pj1-x1029.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This series contains two fixes for the RISC-V IOMMU implementation:\n\n1. Fix a bug in the HPM (Hardware Performance Monitor) timer setup where\n irq_overflow_left was not properly reset, causing stale values from\n previous timer setups to affect new timer behavior.\n\n2. Add proper RW1C (Read/Write 1 to Clear) support for the IPSR.PMIP\n (Performance Monitor Interrupt Pending) bit, which was missing from\n the IPSR register implementation.\n\n---\nChange in V2\n Add commit message\n\nJay Chang (2):\n hw/riscv/riscv-iommu-hpm: Fix irq_overflow_left residual value bug\n hw/riscv/riscv-iommu: Add IPSR.PMIP RW1C support\n\n hw/riscv/riscv-iommu-bits.h | 1 +\n hw/riscv/riscv-iommu-hpm.c | 1 +\n hw/riscv/riscv-iommu.c | 4 ++++\n 3 files changed, 6 insertions(+)" }