Cover Letter Detail
Show a cover letter.
GET /api/covers/2215662/?format=api
{ "id": 2215662, "url": "http://patchwork.ozlabs.org/api/covers/2215662/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/cover/1774403912-210670-1-git-send-email-shawn.lin@rock-chips.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1774403912-210670-1-git-send-email-shawn.lin@rock-chips.com>", "list_archive_url": null, "date": "2026-03-25T01:58:29", "name": "[v5,0/3] PCI Controller event and LTSSM tracepoint support", "submitter": { "id": 66993, "url": "http://patchwork.ozlabs.org/api/people/66993/?format=api", "name": "Shawn Lin", "email": "shawn.lin@rock-chips.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/cover/1774403912-210670-1-git-send-email-shawn.lin@rock-chips.com/mbox/", "series": [ { "id": 497375, "url": "http://patchwork.ozlabs.org/api/series/497375/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497375", "date": "2026-03-25T01:58:29", "name": "PCI Controller event and LTSSM tracepoint support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/497375/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2215662/comments/", "headers": { "Return-Path": "\n <linux-pci+bounces-51002-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=rock-chips.com header.i=@rock-chips.com\n header.a=rsa-sha256 header.s=default header.b=LMJDq85h;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-51002-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com\n header.b=\"LMJDq85h\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=45.254.49.233", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=rock-chips.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=rock-chips.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgVSd2f0Pz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 12:58:57 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 6EBF3302DDEF\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 01:58:55 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id CD50A27A907;\n\tWed, 25 Mar 2026 01:58:53 +0000 (UTC)", "from mail-m49233.qiye.163.com (mail-m49233.qiye.163.com\n [45.254.49.233])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 736262797AC;\n\tWed, 25 Mar 2026 01:58:48 +0000 (UTC)", "from localhost.localdomain (unknown [58.22.7.114])\n\tby smtp.qiye.163.com (Hmail) with ESMTP id 382e59d50;\n\tWed, 25 Mar 2026 09:58:38 +0800 (GMT+08:00)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774403933; cv=none;\n b=AIN9Qi1KgLgwBfUJAnPVOyHH8MQakh7OsmhTqxLbwcHKimhLixaLvb9Sf9AEOosPa/qkDUgoSOpazr5vDowO2GbimuhLg5d1u1LxoJpekm+bC7poklb73y4u8kRdbq++jZg0QrKdx53X+eQ4nNjSDTeCAvt4dFzuKZZwSZYM7fg=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774403933; c=relaxed/simple;\n\tbh=A8l/YdodJU5BcEQaXnFIAnwZZI+l41tuMYRSg+bDics=;\n\th=From:To:Cc:Subject:Date:Message-Id;\n b=LBp/kp0mq5F8SuIU4IU1WFS0NBVNDtfv23XO8iMQKD8PpPgFl35PYM84v9lSGNLdmMehe5kZ1LD4xzldcYwvw+1B48ujGDV8/zM8n/iQMCtYKzOjjI9mfuIubUfqMeQwEpIq719RsOfguff1EeD4ioPLspYQREuR8H5Zkd232OU=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=rock-chips.com;\n spf=pass smtp.mailfrom=rock-chips.com;\n dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com\n header.b=LMJDq85h; arc=none smtp.client-ip=45.254.49.233", "From": "Shawn Lin <shawn.lin@rock-chips.com>", "To": "Manivannan Sadhasivam <mani@kernel.org>,\n\tBjorn Helgaas <bhelgaas@google.com>", "Cc": "linux-rockchip@lists.infradead.org,\n\tlinux-pci@vger.kernel.org,\n\tlinux-trace-kernel@vger.kernel.org,\n\tlinux-doc@vger.kernel.org,\n\tSteven Rostedt <rostedt@goodmis.org>,\n\tShawn Lin <shawn.lin@rock-chips.com>", "Subject": "[PATCH v5 0/3] PCI Controller event and LTSSM tracepoint support", "Date": "Wed, 25 Mar 2026 09:58:29 +0800", "Message-Id": "<1774403912-210670-1-git-send-email-shawn.lin@rock-chips.com>", "X-Mailer": "git-send-email 2.7.4", "X-HM-Tid": "0a9d22b717fc09cckunm61c156f0a55845", "X-HM-MType": "1", "X-HM-Spam-Status": "e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly\n\ttZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQx0aTlYdHUpIThoaTkwaH0tWFRQJFh\n\toXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0\n\thVSktLVUpCS0tZBg++", "DKIM-Signature": "a=rsa-sha256;\n\tb=LMJDq85hB549w4GkDDs7h1WRqkUJJQA763ivP6GKIpLJI4qb/QwHo3g43pKIMjrX88G/INoElzOCsriu+8EVO0dZa0t8H0i1qfk3x8P3tlOW6cFADUH8vQFgrFM/eKPdqQYu7Mro732FYz+nVKnFK+SVQHpcvsA9ylfyYDDR/wI=;\n s=default; c=relaxed/relaxed; d=rock-chips.com; v=1;\n\tbh=iL3uRr9ioLVWGXzImJsgsnPLVa9xILg7XkTqZ91to80=;\n\th=date:mime-version:subject:message-id:from;", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>" }, "content": "This patch-set adds new pci controller event and LTSSM tracepoint used by host drivers\nwhich provide LTSSM trace functionality. The first user is pcie-dw-rockchip with a 256\nBytes FIFO for recording LTSSM transition.\n\nTesting\n=========\n\nThis series was tested on RK3588/RK3588s EVB1 with NVMe SSD connected to PCIe3 and PCIe2\nroot ports.\n\necho 1 > /sys/kernel/debug/tracing/events/pci_controller/pcie_ltssm_state_transition/enable\ncat /sys/kernel/debug/tracing/trace_pipe\n\n # tracer: nop\n #\n # entries-in-buffer/entries-written: 64/64 #P:8\n #\n # _-----=> irqs-off/BH-disabled\n # / _----=> need-resched\n # | / _---=> hardirq/softirq\n # || / _--=> preempt-depth\n # ||| / _-=> migrate-disable\n # |||| / delay\n # TASK-PID CPU# ||||| TIMESTAMP FUNCTION\n # | | | ||||| | |\n kworker/0:0-9 [000] ..... 5.600194: pcie_ltssm_state_transition: dev: a40000000.pcie state: DETECT_ACT rate: Unknown\n kworker/0:0-9 [000] ..... 5.600198: pcie_ltssm_state_transition: dev: a40000000.pcie state: DETECT_WAIT rate: Unknown\n kworker/0:0-9 [000] ..... 5.600199: pcie_ltssm_state_transition: dev: a40000000.pcie state: DETECT_ACT rate: Unknown\n kworker/0:0-9 [000] ..... 5.600201: pcie_ltssm_state_transition: dev: a40000000.pcie state: POLL_ACTIVE rate: Unknown\n kworker/0:0-9 [000] ..... 5.600202: pcie_ltssm_state_transition: dev: a40000000.pcie state: POLL_CONFIG rate: Unknown\n kworker/0:0-9 [000] ..... 5.600204: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_LINKWD_START rate: Unknown\n kworker/0:0-9 [000] ..... 5.600206: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_LINKWD_ACEPT rate: Unknown\n kworker/0:0-9 [000] ..... 5.600207: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_LANENUM_WAI rate: Unknown\n kworker/0:0-9 [000] ..... 5.600208: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_LANENUM_ACEPT rate: Unknown\n kworker/0:0-9 [000] ..... 5.600210: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_COMPLETE rate: Unknown\n kworker/0:0-9 [000] ..... 5.600212: pcie_ltssm_state_transition: dev: a40000000.pcie state: CFG_IDLE rate: Unknown\n kworker/0:0-9 [000] ..... 5.600213: pcie_ltssm_state_transition: dev: a40000000.pcie state: L0 rate: 2.5 GT/s\n kworker/0:0-9 [000] ..... 5.600214: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_LOCK rate: Unknown\n kworker/0:0-9 [000] ..... 5.600216: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_RCVRCFG rate: Unknown\n kworker/0:0-9 [000] ..... 5.600217: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_SPEED rate: Unknown\n kworker/0:0-9 [000] ..... 5.600218: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_LOCK rate: Unknown\n kworker/0:0-9 [000] ..... 5.600220: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ1 rate: Unknown\n kworker/0:0-9 [000] ..... 5.600221: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ2 rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600222: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ3 rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600224: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_LOCK rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600225: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_RCVRCFG rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600226: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_IDLE rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600227: pcie_ltssm_state_transition: dev: a40000000.pcie state: L0 rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600228: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_LOCK rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600229: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_RCVRCFG rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600231: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_IDLE rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600232: pcie_ltssm_state_transition: dev: a40000000.pcie state: L0 rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600233: pcie_ltssm_state_transition: dev: a40000000.pcie state: L123_SEND_EIDLE rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600234: pcie_ltssm_state_transition: dev: a40000000.pcie state: L1_IDLE rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600236: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_LOCK rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600237: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_RCVRCFG rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600238: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_IDLE rate: 8.0 GT/s\n kworker/0:0-9 [000] ..... 5.600239: pcie_ltssm_state_transition: dev: a40000000.pcie state: L0 rate: 8.0 GT/s\n\n\nChanges in v5:\n- rebase\n- use EM/EMe instead\n- remove reg/unreg function and back to use TRACE_EVENT\n- use trace_pcie_ltssm_state_transition_enabled()\n\nChanges in v4:\n- use TRACE_EVENT_FN to notify when to start and stop the tracepoint,\n and export pci_ltssm_tp_enabled() for host drivers to use\n- skip trace if pci_ltssm_tp_enabled() is false.(Steven)\n- wrap into 80 columns(Bjorn)\n\nChanges in v3:\n- add TRACE_DEFINE_ENUM for all enums(Steven Rostedt)\n- Add toctree entry in Documentation/trace/index.rst(Bagas Sanjaya)\n- fix mismatch section underline length(Bagas Sanjaya)\n- Make example snippets in code block(Bagas Sanjaya)\n- warp context into 80 columns and fix the file name(Bjorn)\n- reorder variables(Mani)\n- rename loop to i; rename en to enable(Mani)\n- use FIELD_GET(Mani)\n- add comment about how the FIFO works(Mani)\n\nChanges in v2:\n- use tracepoint\n\nShawn Lin (3):\n PCI: trace: Add PCI controller LTSSM transition tracepoint\n Documentation: tracing: Add PCI controller event documentation\n PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support\n\n Documentation/trace/events-pci-controller.rst | 42 ++++++++++\n Documentation/trace/index.rst | 1 +\n drivers/pci/controller/dwc/pcie-dw-rockchip.c | 111 ++++++++++++++++++++++++++\n drivers/pci/trace.c | 1 +\n include/trace/events/pci_controller.h | 58 ++++++++++++++\n 5 files changed, 213 insertions(+)\n create mode 100644 Documentation/trace/events-pci-controller.rst\n create mode 100644 include/trace/events/pci_controller.h" }