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{ "id": 2202549, "url": "http://patchwork.ozlabs.org/api/covers/2202549/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260227203627.932864-1-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260227203627.932864-1-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-27T20:35:50", "name": "[v3,00/37] Hexagon system emulation - Part 1/3", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260227203627.932864-1-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 493813, "url": "http://patchwork.ozlabs.org/api/series/493813/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=493813", "date": "2026-02-27T20:35:57", "name": "Hexagon system emulation - Part 1/3", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/493813/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2202549/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=D1NGOxro;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com 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"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This is Part 1 of the hexagon system emulation (sysemu) patch series,\nproviding the foundational target infrastructure needed for full-system\nemulation of the Qualcomm Hexagon DSP.\n\nChanges since v2:\n - Rebased onto latest tip\n - Refactored TLB from embedded CPUHexagonTLBContext struct to a proper\n QOM SysBusDevice (TYPE_HEXAGON_TLB).\n - Folded \"Add initial MMU model\" into \"Add stubs for modify_ssr/\n get_exe_mode\" since the TLB QOM device, hex_mmu.h, and hex_mmu.c\n are now introduced together\n - Folded \"Add gdb support for sys regs\" into earlier patches\n - Significantly reduced attribute definitions in attribs_def.h.inc\n - Added #ifndef CONFIG_USER_ONLY guards around hexagon_sregnames[]\n and hexagon_gregnames[] extern declarations in internal.h\n - Adapted to tip removing gen_tcg_func_table.py; added empty stubs\n for tag_ignored instructions in gen_tcg_funcs.py\n - Absorbed \"initialize sys/guest reg TCGvs\" commit into \"Add TCG\n values for sreg, greg\"\n - Used hex_dump_mmu_entry() helper in MMU model for cleaner TLB dump\n - Cleaned up system register names (s59-s63 placeholder convention)\n - Fixed 0xffffffffULL -> 0xffffffff for UINT32 properties\n\nPrevious versions:\n v2: https://lore.kernel.org/qemu-devel/20250902034715.1947718-1-brian.cain@oss.qualcomm.com/\n v1: https://lore.kernel.org/qemu-devel/20250301052628.1011210-1-brian.cain@oss.qualcomm.com/\n\nBrian Cain (37):\n docs: Add hexagon sysemu docs\n docs/system: Add hexagon CPU emulation\n target/hexagon: Fix badva reference, delete CAUSE\n target/hexagon: Add missing A_CALL attr, hintjumpr to multi_cof\n target/hexagon: Handle system/guest registers in gen_analyze_funcs.py\n and hex_common.py\n target/hexagon: Make gen_exception_end_tb non-static\n target/hexagon: Switch to tag_ignore(), generate via\n get_{user,sys}_tags()\n target/hexagon: Add system event, cause codes\n target/hexagon: Add privilege check, use tag_ignore()\n target/hexagon: Add memory order definition\n target/hexagon: Add a placeholder fp exception\n target/hexagon: Add guest, system reg number defs\n target/hexagon: Add guest, system reg number state\n target/hexagon: Add TCG values for sreg, greg\n target/hexagon: Add guest/sys reg writes to DisasContext\n target/hexagon: Add imported macro, attr defs for sysemu\n target/hexagon: Add new macro definitions for sysemu\n target/hexagon: Add handlers for guest/sysreg r/w\n target/hexagon: Add placeholder greg/sreg r/w helpers\n target/hexagon: Add vmstate representation\n target/hexagon: Make A_PRIV, \"J2_trap*\" insts need_env()\n target/hexagon: Define register fields for system regs\n target/hexagon: Implement do_raise_exception()\n target/hexagon: Add system reg insns\n target/hexagon: Add sysemu TCG overrides\n target/hexagon: Add implicit attributes to sysemu macros\n target/hexagon: Add TCG overrides for int handler insts\n target/hexagon: Add TCG overrides for thread ctl\n target/hexagon: Add TCG overrides for rte, nmi\n target/hexagon: Add sreg_{read,write} helpers\n target/hexagon: Add locks, id, next_PC to state\n target/hexagon: Add a TLB count property\n target/hexagon: Add {TLB,k0}lock, cause code, wait_next_pc\n target/hexagon: Add stubs for modify_ssr/get_exe_mode\n target/hexagon: Add clear_wait_mode() definition\n target/hexagon: Define f{S,G}ET_FIELD macros\n target/hexagon: Add hex_interrupts support\n\n MAINTAINERS | 3 +\n docs/devel/hexagon-sys.rst | 112 +++++\n docs/devel/index-internals.rst | 1 +\n docs/system/hexagon/cdsp.rst | 12 +\n docs/system/hexagon/emulation.rst | 15 +\n docs/system/target-hexagon.rst | 103 +++++\n docs/system/targets.rst | 1 +\n include/hw/hexagon/hexagon_tlb.h | 47 ++\n target/hexagon/cpu-param.h | 9 +\n target/hexagon/cpu.h | 69 ++-\n target/hexagon/cpu_bits.h | 82 +++-\n target/hexagon/cpu_helper.h | 45 ++\n target/hexagon/gen_tcg.h | 9 +\n target/hexagon/gen_tcg_sys.h | 102 +++++\n target/hexagon/helper.h | 22 +\n target/hexagon/hex_interrupts.h | 15 +\n target/hexagon/hex_mmu.h | 25 ++\n target/hexagon/hex_regs.h | 115 +++++\n target/hexagon/internal.h | 17 +\n target/hexagon/macros.h | 35 +-\n target/hexagon/sys_macros.h | 237 ++++++++++\n target/hexagon/translate.h | 43 ++\n target/hexagon/attribs_def.h.inc | 49 ++-\n target/hexagon/reg_fields_def.h.inc | 96 ++++\n hw/hexagon/hexagon_tlb.c | 457 +++++++++++++++++++\n linux-user/hexagon/cpu_loop.c | 16 +\n target/hexagon/arch.c | 5 +\n target/hexagon/cpu.c | 57 ++-\n target/hexagon/cpu_helper.c | 91 ++++\n target/hexagon/genptr.c | 151 +++++++\n target/hexagon/hex_interrupts.c | 332 ++++++++++++++\n target/hexagon/hex_mmu.c | 273 ++++++++++++\n target/hexagon/machine.c | 32 ++\n target/hexagon/op_helper.c | 139 +++++-\n target/hexagon/translate.c | 32 +-\n target/hexagon/gen_analyze_funcs.py | 21 +-\n target/hexagon/gen_helper_funcs.py | 26 +-\n target/hexagon/gen_helper_protos.py | 23 +-\n target/hexagon/gen_idef_parser_funcs.py | 2 +\n target/hexagon/gen_op_attribs.py | 2 +-\n target/hexagon/gen_opcodes_def.py | 5 +-\n target/hexagon/gen_tcg_funcs.py | 35 +-\n target/hexagon/hex_common.py | 176 +++++++-\n target/hexagon/imported/encode_pp.def | 128 +++++-\n target/hexagon/imported/macros.def | 558 ++++++++++++++++++++++++\n target/hexagon/imported/system.idef | 244 ++++++++++-\n target/hexagon/meson.build | 14 +-\n 47 files changed, 3978 insertions(+), 105 deletions(-)\n create mode 100644 docs/devel/hexagon-sys.rst\n create mode 100644 docs/system/hexagon/cdsp.rst\n create mode 100644 docs/system/hexagon/emulation.rst\n create mode 100644 docs/system/target-hexagon.rst\n create mode 100644 include/hw/hexagon/hexagon_tlb.h\n create mode 100644 target/hexagon/cpu_helper.h\n create mode 100644 target/hexagon/gen_tcg_sys.h\n create mode 100644 target/hexagon/hex_interrupts.h\n create mode 100644 target/hexagon/hex_mmu.h\n create mode 100644 target/hexagon/sys_macros.h\n create mode 100644 hw/hexagon/hexagon_tlb.c\n create mode 100644 target/hexagon/cpu_helper.c\n create mode 100644 target/hexagon/hex_interrupts.c\n create mode 100644 target/hexagon/hex_mmu.c\n create mode 100644 target/hexagon/machine.c\n mode change 100755 => 100644 target/hexagon/imported/macros.def" }