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{ "id": 2197134, "url": "http://patchwork.ozlabs.org/api/covers/2197134/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260217080102.206581-2-sunlightlinux@gmail.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260217080102.206581-2-sunlightlinux@gmail.com>", "list_archive_url": null, "date": "2026-02-17T08:00:56", "name": "[RFC,0/3] PCI: Add PCIe Gen 7 (128 GT/s) speed support", "submitter": { "id": 92653, "url": "http://patchwork.ozlabs.org/api/people/92653/?format=api", "name": "Ionut Nechita (Sunlight Linux)", "email": "sunlightlinux@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260217080102.206581-2-sunlightlinux@gmail.com/mbox/", "series": [ { "id": 492389, "url": "http://patchwork.ozlabs.org/api/series/492389/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492389", "date": "2026-02-17T08:00:56", "name": "PCI: Add PCIe Gen 7 (128 GT/s) speed support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492389/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2197134/comments/", "headers": { "Return-Path": "\n <linux-pci+bounces-47421-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=RdRFFhAb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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Wysocki\" <rafael@kernel.org>,\n Daniel Lezcano <daniel.lezcano@linaro.org>", "Cc": "Zhang Rui <rui.zhang@intel.com>,\n\tLukasz Luba <lukasz.luba@arm.com>,\n\tLukas Wunner <lukas@wunner.de>,\n\tIonut Nechita <sunlightlinux@gmail.com>,\n\tlinux-pci@vger.kernel.org,\n\tlinux-pm@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tIonut Nechita <ionut_n2001@yahoo.com>", "Subject": "[RFC PATCH 0/3] PCI: Add PCIe Gen 7 (128 GT/s) speed support", "Date": "Tue, 17 Feb 2026 10:00:56 +0200", "Message-ID": "<20260217080102.206581-2-sunlightlinux@gmail.com>", "X-Mailer": "git-send-email 2.53.0", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Ionut Nechita <ionut_n2001@yahoo.com>\n\nThis RFC series adds initial kernel support for PCIe Gen 7 128 GT/s\nlink speed, following the same pattern used for Gen 6 (64 GT/s).\n\nPCIe Gen 7 doubles the per-lane data rate to 128 GT/s using PAM4\nsignaling with mandatory Flit mode encoding (1:1, no overhead),\nproviding up to 256 GB/s unidirectional (512 GB/s bi-directional)\nbandwidth on an x16 link. The specification was announced by PCI-SIG\nin 2022 and targeted for member release in 2025.\n\nThe series covers:\n\n Patch 1: UAPI register definitions (LNKCAP, LNKCAP2, LNKCTL2) and\n pci_bus_speed enum. Widens supported_speeds from u8 to u16\n to accommodate the expanded Supported Link Speeds Vector.\n\n Patch 2: Core PCI infrastructure - speed detection macros, bandwidth\n calculation with 1:1 Flit mode encoding, link speed table,\n display string, and a pcie_speed_requires_flit() helper\n with Flit mode diagnostic warning for Gen 6+ speeds.\n\n Patch 3: Subsystem updates for bandwidth control (bwctrl), port\n driver, and PCIe thermal cooling.\n\nNot included in this series (not yet defined in the specification):\n - Equalization presets for 128 GT/s (PCI_EXT_CAP_ID_PL_128GT)\n - DesignWare controller preset programming for Gen 7\n\nThis is marked as RFC since no PCIe Gen 7 hardware exists yet to\nvalidate the implementation. The register encoding values (LNKCAP\nSLS=0x7, LNKCAP2 SLS bit 6, LNKCTL2 TLS=0x7) follow the sequential\npattern established by prior generations and are subject to change\nwhen the final specification is published.\n\nTested: compile-tested only (no hardware available).\n\nIonut Nechita (3):\n PCI: Add PCIe Gen 7 (128 GT/s) register and speed definitions\n PCI: Add PCIe Gen 7 (128 GT/s) speed detection and reporting\n PCI: Update bandwidth control and thermal cooling for Gen 7 (128 GT/s)\n\n drivers/pci/pci.c | 7 +++++--\n drivers/pci/pci.h | 28 ++++++++++++++++++++++------\n drivers/pci/pcie/bwctrl.c | 7 ++++---\n drivers/pci/pcie/portdrv.c | 2 +-\n drivers/pci/probe.c | 3 ++-\n drivers/thermal/pcie_cooling.c | 1 +\n include/linux/pci.h | 3 ++-\n include/uapi/linux/pci_regs.h | 3 +++\n 8 files changed, 40 insertions(+), 14 deletions(-)" }