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{ "id": 2197105, "url": "http://patchwork.ozlabs.org/api/covers/2197105/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260217-master-v1-0-727e26cdfaf5@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260217-master-v1-0-727e26cdfaf5@nvidia.com>", "list_archive_url": null, "date": "2026-02-17T05:54:40", "name": "[0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/cover/20260217-master-v1-0-727e26cdfaf5@nvidia.com/mbox/", "series": [ { "id": 492373, "url": "http://patchwork.ozlabs.org/api/series/492373/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=492373", "date": "2026-02-17T05:54:40", "name": "PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492373/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2197105/comments/", "headers": { "Return-Path": "\n <linux-tegra+bounces-11967-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=JsFdanci;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "Niklas Cassel <cassel@kernel.org>, Vidya Sagar <vidyas@nvidia.com>,\n Manivannan Sadhasivam <mani@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84sk?=\n\t=?utf-8?q?i?= <kwilczynski@kernel.org>,\n \"Kishon Vijay Abraham I\" <kishon@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n \"Lorenzo Pieralisi\" <lpieralisi@kernel.org>, Rob Herring <robh@kernel.org>,\n \"Thierry Reding\" <thierry.reding@gmail.com>,\n Jonathan Hunter <jonathanh@nvidia.com>, Arnd Bergmann <arnd@arndb.de>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,\n Masami Hiramatsu <mhiramat@kernel.org>", "CC": "Manikanta Maddireddy <mmaddireddy@nvidia.com>,\n\t<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>", "Subject": "[PATCH 0/4] PCI: endpoint: Add BAR_DISABLED support to PCI endpoint\n framework", "Date": "Tue, 17 Feb 2026 11:24:40 +0530", "Message-ID": "<20260217-master-v1-0-727e26cdfaf5@nvidia.com>", "X-Mailer": [ "git-send-email 2.34.1", "b4 0.14.3" ], "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; 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The host-side pci_endpoint_test driver\nstill ioremaps all enabled BARs and runs BAR read/write tests on them. Writing to\nBAR2 (MSI-X table) or BAR4 (DMA registers) corrupts controller state and breaks\nCONSECUTIVE_BAR_TEST. A prior fix reset all BARs in the EPC .init(), so only\nBAR0 was visible to the host—tests passed but 64-bit BAR 2 and BAR 4 were no\nlonger available for real use (e.g. host DMA via BAR4).\n\nThis series addresses that by:\n\n1) Adding BAR_DISABLED and clarifying BAR_RESERVED in the PCI endpoint core.\n BAR_RESERVED is used for (a) HW-backed BARs (MSI-X, DMA) that the EPC may\n leave enabled, and (b) the second register of a 64-bit BAR. BAR_DISABLED is\n for unused BARs that the EPC must disable in .init() and the EPF must not\n use. pci_epc_get_next_free_bar() treats both as not free.\n\n2) Updating Tegra194 endpoint to use three 64-bit BARs at indices 0, 2, and 4:\n BAR0+BAR1 for EPF test/data, BAR2+BAR3 for MSI-X table, BAR4+BAR5 for DMA.\n Only BAR0 and BAR1 are reset in .init(); BAR2/BAR3 and BAR4/BAR5 stay\n enabled so the host can use MSI-X and DMA.\n\n3) Adding a BAR skip mask to pci_endpoint_test so endpoints can skip the\n destructive BAR test on HW-backed BARs. Tegra EP test data skips BAR1–BAR5\n (test only BAR0). Adding NVIDIA Tegra194 EP (0x1AD4) and Tegra234 EP (0x229B)\n to the pci_endpoint_test_tbl so the host driver can bind and run tests\n without corrupting MSI-X or DMA registers.\n\n4) Converting unused BAR_RESERVED to BAR_DISABLED in the Uniphier Pro5 endpoint\n (BAR4 and BAR5); BAR1 and BAR3 remain BAR_RESERVED as the high halves of\n 64-bit BAR0 and BAR2.\n\nWith this, CONSECUTIVE_BAR_TEST and DMA tests pass while Tegra194 keeps 64-bit\nBAR 2 (MSI-X) and BAR 4 (DMA) enabled for host use.\n\npci_endpoint_test results on Tegra234 SoC,\n\n$ ./pci_endpoint_test -f pci_ep_bar -f pci_ep_basic -v memcpy -T COPY_TEST -V dma\nTAP version 13\n1..13\n Starting 13 tests from 8 test cases.\n RUN pci_ep_bar.BAR0.BAR_TEST ...\n OK pci_ep_bar.BAR0.BAR_TEST\nok 1 pci_ep_bar.BAR0.BAR_TEST\n RUN pci_ep_bar.BAR1.BAR_TEST ...\n OK pci_ep_bar.BAR1.BAR_TEST\nok 2 pci_ep_bar.BAR1.BAR_TEST\n RUN pci_ep_bar.BAR2.BAR_TEST ...\n OK pci_ep_bar.BAR2.BAR_TEST\nok 3 pci_ep_bar.BAR2.BAR_TEST\n RUN pci_ep_bar.BAR3.BAR_TEST ...\n OK pci_ep_bar.BAR3.BAR_TEST\nok 4 pci_ep_bar.BAR3.BAR_TEST\n RUN pci_ep_bar.BAR4.BAR_TEST ...\n OK pci_ep_bar.BAR4.BAR_TEST\nok 5 pci_ep_bar.BAR4.BAR_TEST\n RUN pci_ep_bar.BAR5.BAR_TEST ...\n OK pci_ep_bar.BAR5.BAR_TEST\nok 6 pci_ep_bar.BAR5.BAR_TEST\n RUN pci_ep_basic.CONSECUTIVE_BAR_TEST ...\n OK pci_ep_basic.CONSECUTIVE_BAR_TEST\nok 7 pci_ep_basic.CONSECUTIVE_BAR_TEST\n RUN pci_ep_basic.LEGACY_IRQ_TEST ...\n OK pci_ep_basic.LEGACY_IRQ_TEST\nok 8 pci_ep_basic.LEGACY_IRQ_TEST\n RUN pci_ep_basic.MSI_TEST ...\n SKIP MSI17 is disabled\n OK pci_ep_basic.MSI_TEST\nok 9 pci_ep_basic.MSI_TEST # SKIP MSI17 is disabled\n RUN pci_ep_basic.MSIX_TEST ...\n pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)\n pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X1\n pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)\n pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X2\n pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)\n pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X3\n pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)\n pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X4\n pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)\n pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X5\n pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)\n pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X6\n pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)\n pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X7\n pci_endpoint_test.c:144:MSIX_TEST:Expected 0 (0) == ret (-5)\n pci_endpoint_test.c:144:MSIX_TEST:Test failed for MSI-X8\n SKIP MSI-X9 is disabled\n OK pci_ep_basic.MSIX_TEST\nok 10 pci_ep_basic.MSIX_TEST # SKIP MSI-X9 is disabled\n RUN pci_ep_data_transfer.memcpy.READ_TEST ...\n OK pci_ep_data_transfer.memcpy.READ_TEST\nok 11 pci_ep_data_transfer.memcpy.READ_TEST\n RUN pci_ep_data_transfer.memcpy.WRITE_TEST ...\n OK pci_ep_data_transfer.memcpy.WRITE_TEST\nok 12 pci_ep_data_transfer.memcpy.WRITE_TEST\n RUN pci_ep_data_transfer.memcpy.COPY_TEST ...\n OK pci_ep_data_transfer.memcpy.COPY_TEST\nok 13 pci_ep_data_transfer.memcpy.COPY_TEST\n PASSED: 13 / 13 tests passed.\n 2 skipped test(s) detected. Consider enabling relevant config options to improve coverage.\n Totals: pass:11 fail:0 xfail:0 xpass:0 skip:2 error:0\n\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nManikanta Maddireddy (4):\n PCI: endpoint: Add BAR_DISABLED and document BAR_RESERVED semantics\n PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode\n misc: pci_endpoint_test: Add BAR skip mask and NVIDIA Tegra EP device IDs\n PCI: uniphier-ep: Convert unused BAR_RESERVED to BAR_DISABLED for Pro5\n\n drivers/misc/pci_endpoint_test.c | 34 ++++++++++++++++++++++++---\n drivers/pci/controller/dwc/pcie-tegra194.c | 26 +++++++++++---------\n drivers/pci/controller/dwc/pcie-uniphier-ep.c | 8 +++----\n drivers/pci/endpoint/pci-epc-core.c | 5 ++--\n include/linux/pci-epc.h | 13 ++++++++--\n 5 files changed, 64 insertions(+), 22 deletions(-)\n---\nbase-commit: 6f54fb70124423ec417b5efe81f8ced5b9891d62\nchange-id: 20260217-master-27db95eb02bd\n\nBest regards," }