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{ "id": 2196785, "url": "http://patchwork.ozlabs.org/api/covers/2196785/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260216105547.13457-1-devendra.verma@amd.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260216105547.13457-1-devendra.verma@amd.com>", "list_archive_url": null, "date": "2026-02-16T10:55:44", "name": "[RESEND,v10,0/2] Add AMD MDB Endpoint and non-LL mode Support", "submitter": { "id": 91622, "url": "http://patchwork.ozlabs.org/api/people/91622/?format=api", "name": "Devendra K Verma", "email": "devendra.verma@amd.com" }, "mbox": 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<linux-pci@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, <michal.simek@amd.com>,\n\t<Devendra.Verma@amd.com>", "Subject": "[PATCH RESEND v10 0/2] Add AMD MDB Endpoint and non-LL mode Support", "Date": "Mon, 16 Feb 2026 16:25:44 +0530", "Message-ID": "<20260216105547.13457-1-devendra.verma@amd.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF000044F9:EE_|SA1PR12MB8699:EE_", "X-MS-Office365-Filtering-Correlation-Id": "65375e49-28e2-48e8-00a7-08de6d49f303", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": 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"X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCO1PEPF000044F9.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB8699" }, "content": "This series of patch support the following:\n\n - AMD MDB Endpoint Support, as part of this patch following are\n added:\n o AMD supported device ID and vendor ID (Xilinx)\n o AMD MDB specific driver data\n o AMD specific VSEC capabilities to retrieve the base of\n phys address of MDB side DDR\n o Logic to assign the offsets to LL and data blocks if\n more number of channels are enabled than configured\n in the given pci_data struct.\n\n - Addition of non-LL mode\n o The IP supported non-LL mode functions\n o Flexibility to choose non-LL mode via dma_slave_config\n param peripheral_config, by the client for all the vendors\n using HDMA IP.\n o Allow IP utilization if LL mode is not available\n\nDevendra K Verma (2):\n dmaengine: dw-edma: Add AMD MDB Endpoint Support\n dmaengine: dw-edma: Add non-LL mode\n\n drivers/dma/dw-edma/dw-edma-core.c | 35 +++-\n drivers/dma/dw-edma/dw-edma-core.h | 1 +\n drivers/dma/dw-edma/dw-edma-pcie.c | 220 +++++++++++++++++++++++---\n drivers/dma/dw-edma/dw-hdma-v0-core.c | 65 +++++++-\n drivers/dma/dw-edma/dw-hdma-v0-regs.h | 1 +\n include/linux/dma/edma.h | 1 +\n 6 files changed, 301 insertions(+), 22 deletions(-)" }