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helo=lewvzet200.ext.ti.com; pr=C", "From": "Siddharth Vadapalli <s-vadapalli@ti.com>", "To": "<trini@konsulko.com>, <m-chawdhry@ti.com>, <c-vankar@ti.com>,\n <neil.armstrong@linaro.org>, <marek.vasut+renesas@mailbox.org>,\n <u-kumar1@ti.com>, <j-keerthy@ti.com>, <semen.protsenko@linaro.org>,\n <afd@ti.com>, <anshuld@ti.com>, <peng.fan@nxp.com>, <ahalaney@redhat.com>,\n <mkorpershoek@kernel.org>, <n-francis@ti.com>", "CC": "<u-boot@lists.denx.de>, <srk@ti.com>, <s-vadapalli@ti.com>", "Subject": "[PATCH v5 00/10] Add PCIe Boot support for TI J784S4 SoC", "Date": "Mon, 16 Feb 2026 15:58:28 +0530", "Message-ID": "<20260216102858.2745657-1-s-vadapalli@ti.com>", "X-Mailer": "git-send-email 2.51.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-C2ProcessedOrg": "333ef613-75bf-4e12-a4b1-8e3623f5dcea", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF000066ED:EE_|CH3PR10MB7504:EE_", "X-MS-Office365-Filtering-Correlation-Id": "125549d3-173c-4387-0174-08de6d460105", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|82310400026|1800799024|376014|36860700013|921020;", "X-Microsoft-Antispam-Message-Info": "\n Ep+/lVt/pKqWJYFSvTojawaVwMjYmpB45ODRu1hq55z4KPk+cW/g3SHknjzq4iKwGHV9huqE+ilVwA+ZXOIwZF7s5zj4tVnhwlgQfe94Zb+K36Zfrb9i4aj5sKkJeNkA6ozmZHAxptU+tL/+Zm+2nr9Rd+zM4Q+/CiRBY7iif9Zo4drSGj3TtClSbslSFn3Rd2nG+F12EzVOVbwK9AKv/ug/GKX4J6D5kTakRtUB8YEzk0zIkZX+aEKFeJlweMqQ+8xzvRkZFgFIduXbIcj9urrh9qSvVAuto3poKAg/BLohLNaraSIfW50XQKTThZeOB00jpJHGOcvCDiutQhtdmchthHm2xR5C0CA5CQ7WFmNjGcWcBAnAeaaP9Ed0iAsvMxK+oWo1XNVaAPfhTJ27X0SQekF8ozMeG5PnQBtutM2BqbayCmygzMG9s8T5Kx6fyc9lqR+9/HwBumV/PV9xOPQejyDFdflug1pPbSyU9HfCrf6cecLofNF8ccPG7YS5QxsPh8vFcjcdolNGjF/HsMmnmeysx2YwEXhriiRgkojzhWpyN35zFzjseITXMimHdawxdWheib9b7SDZqANRc63x/pgep7cUqy//lYYk+LkRy9wd9fKW5+HcTgpLSH8dNsmd4zBzSf+0rgBrd+3zklW71SHbpHSRjP5VInsVzK9/K30GAiPgNC1XOxcIT3bK6Zku2jZhFB7eyc4h62jw9mlH61zBj8f4EWIsuqmep6TzSRpjtmHgMPsYw5pwgkzafFAdq5l5O/Pg3QbqXHusNUGstX5ucJVjZdyb2+HAnYqp7BhJLqwrDef23nRyjCG7p5t8H8WeCfOOPcA5+h6zXjNL5DWx3vES8nolOn2DUhB4RKik1s+5w5SND2NIT+9FVBkukUlxK6+ymDOMr7l/8NxxOgIYE/W2Aprf70w2qFZJZqCbpXD3yb55y/c/c3wIloShS5tpD6ymqA3I0tgg/6RDI7O4LONKVSlEKO+wgNaEfEBsbsGUXyhsURo9LsD0MeYUsJg6nITMbv94N6MCzicUkf1k8cO0fRYGi2kOIGJnmhhimG9FzoFcCfu56/hlfKk5cimawx67XCBSJL3OEB7Q0Fx+YMDQwbcpYlM7KrtzTspFJs8Mr80IxrgmgtFKz+nus2X6UygJ9EzOSOQ9QWxwgQYSM20KDLMnRhZObgDfnAVLuuPx96DjRqJ+DR5IzIwRiy4hNZz4hUUda3Dz9DOoO9sFu+Tcg56M9Ni5kywNJoznFNFW5x1o/QIof0WKAh7A+1m4TCeROXkfLlptz14YNw6bmjdtR0GWMS/vSGr2vKlznVAD8Mmh4SzUQOMf45kqBtm2Gx3sc2WWINoeTdhKh4sKjcvf70ghMbL82o0Y9C33m1H8ZAw5uPVTPUA1XD0Avl3Dl3+4YGnqOA32gOBIgPP89Ziqyw4deRHhsAuBEqfyQwNh33J1kWMd7OpS2B22Q4ah/jla9BSVO85PXJEpQ5HC8cuoNg0RyUapcfm2rbVwBTodtScW94cInYjuAObocBDQmrwfpytmFuVJygjk0OIaU8ycV5tQT9GI+Yphbh2QPjxXjADasyLrAeIaal3V2RvYZTyX60s3O6w+R9MmciA9UcjPreRUPaApzkY=", "X-Forefront-Antispam-Report": "CIP:198.47.23.194; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:lewvzet200.ext.ti.com; PTR:InfoDomainNonexistent;\n CAT:NONE;\n SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013)(921020);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n WsrO0fQM/UqxVhguY6lT0G8vS5VY3hu+SgoWDYiU6ksdZxUurpPGAO24xrkaaAR4GqXRtgjIennmUj7mu65tPq1YgNtaFhRM4k81/CLeH6XeZoq8Qu7HnWy0QEbRHsoOJXjV6IYW+O+aVJhJoyW1lPj972Tv3PvMimzE6bLah6TqHTGTz9KpeArttXaiElx0hVQc7FlSumccn/m3ThYLDDy+YWMd/HToCt/I2KOoMY8WoW3DAN+iYQzC05YtFPRnGEzFWcFmm/voNGRGG1qkwxAL0xQagv7D936YnNMr4VNG2GqsLIFSSo+figZE4UPOEGXQt1MNnQ/Ujpg7G/iqsgm3+Tb5WTlqGkpddyQDQ/0/kf62eMHUxG18rPAV0Hc8nPJ2jAhdDBDCWAjIiO186kuhz+YS/pFdtt/aApnwXtSuWheiM0m/CrIYPopBaBnR", "X-OriginatorOrg": "ti.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Feb 2026 10:27:36.4111 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 125549d3-173c-4387-0174-08de6d460105", "X-MS-Exchange-CrossTenant-Id": "e5b49634-450b-4709-8abb-1e2b19b982b7", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7; Ip=[198.47.23.194];\n Helo=[lewvzet200.ext.ti.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1PEPF000066ED.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR10MB7504", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Hello,\n\nThis series adds PCIe endpoint boot support for the TI J784S4 SoC.\nSeries is based on commit\nf9ffeec4bdc board: toradex: Make A53 get RAM size from DT in K3 boards\nof the master branch of U-Boot.\n\nv4 of this series is at:\nhttps://patchwork.ozlabs.org/project/uboot/cover/20251201110103.845413-1-h-salunke@ti.com/\nChanges since v4:\n- Addressed Udit's feedback:\n i) Patch 6 has been updated by limiting changes to disabling CONFIG_SPL_PCI_ENDPOINT\n and CONFIG_SPL_PHY (CONFIG_PCIE_CDNS_TI_EP, CONFIG_SPL_PHY_CADENCE_TORRENT and\n CONFIG_SPL_PHY_J721E_WIZ don't need to be disabled as pointed out by Udit).\n ii) Commit message of patch 8 has been updated to indicate that although PCIe Boot\n is supported in Hardware for J742S2 SoC, it is not yet enabled in Software.\n iii) Documentation in patch 10 has been updated with complete set of device-tree\n changes included and the C Program to transfer bootloaders has also been\n simplified and documented with the usage of appropriate variable names.\n\nPCIe Boot Logs (J784S4-EVM running Linux as Root-Complex transfers\nbootloaders to another J784S4-EVM configured for PCIe Boot):\nhttps://gist.github.com/Siddharth-Vadapalli-at-TI/2d157003818441fe79a139d0dec1058a\n\nRegards,\nSiddharth.\n\nHrushikesh Salunke (10):\n arm: mach-k3: j784s4: Update SoC autogen data to enable PCIe boot\n phy: cadence: Add config to enable Cadence Torrent PHY at SPL stage\n phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage\n configs: j784s4_evm_r5_defconfig: Enable configs for PCIe boot\n configs: j784s4_evm_a72_defconfig: Enable configs for PCIe boot\n configs: am69_sk_r5_defconfig: Disable PCIe boot configs\n configs: am69_sk_a72_defconfig: Disable PCIe boot configs\n configs: j742s2_evm_r5_defconfig: Disable PCIe boot configs\n configs: j742s2_evm_a72_defconfig: Disable PCIe boot configs\n docs: board: ti: j784s4_evm: Add PCIe boot documentation\n\n arch/arm/mach-k3/r5/j784s4/clk-data.c | 184 +++++++++++++++-\n arch/arm/mach-k3/r5/j784s4/dev-data.c | 45 ++--\n configs/am69_sk_a72_defconfig | 3 +\n configs/am69_sk_r5_defconfig | 6 +\n configs/j742s2_evm_a72_defconfig | 4 +\n configs/j742s2_evm_r5_defconfig | 6 +\n configs/j784s4_evm_a72_defconfig | 7 +\n configs/j784s4_evm_r5_defconfig | 13 ++\n doc/board/ti/j784s4_evm.rst | 305 ++++++++++++++++++++++++++\n drivers/phy/cadence/Kconfig | 7 +\n drivers/phy/ti/Kconfig | 10 +\n 11 files changed, 562 insertions(+), 28 deletions(-)" }