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{ "id": 2196579, "url": "http://patchwork.ozlabs.org/api/covers/2196579/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260215084950.4657-1-ankita@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260215084950.4657-1-ankita@nvidia.com>", "list_archive_url": null, "date": "2026-02-15T08:49:47", "name": "[v3,0/3] hw/vfio: Enable hugepfnmap for non-power-of-2 device memory regions", "submitter": { "id": 86155, "url": "http://patchwork.ozlabs.org/api/people/86155/?format=api", "name": "Ankit Agrawal", "email": "ankita@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260215084950.4657-1-ankita@nvidia.com/mbox/", "series": [ { "id": 492205, "url": "http://patchwork.ozlabs.org/api/series/492205/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492205", "date": "2026-02-15T08:49:48", "name": "hw/vfio: Enable hugepfnmap for non-power-of-2 device memory regions", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/492205/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2196579/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=jD99eldl;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=52.101.193.43;\n envelope-from=ankita@nvidia.com;\n helo=CH1PR05CU001.outbound.protection.outlook.com" ], "From": "<ankita@nvidia.com>", "To": "<ankita@nvidia.com>, <vsethi@nvidia.com>, <jgg@nvidia.com>,\n <skolothumtho@nvidia.com>, <alex@shazbot.org>, <clg@redhat.com>", "CC": "<aniketa@nvidia.com>, <cjia@nvidia.com>, <kwankhede@nvidia.com>,\n <targupta@nvidia.com>, <zhiw@nvidia.com>, <mochs@nvidia.com>,\n <kjaju@nvidia.com>, <qemu-devel@nongnu.org>", "Subject": "[PATCH v3 0/3] hw/vfio: Enable hugepfnmap for non-power-of-2 device\n memory regions", "Date": "Sun, 15 Feb 2026 08:49:47 +0000", "Message-ID": "<20260215084950.4657-1-ankita@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000C6185:EE_|SJ1PR12MB6220:EE_", "X-MS-Office365-Filtering-Correlation-Id": "2983fc76-4156-4949-e0bf-08de6c6f33f9", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|82310400026|36860700013|376014|13003099007;", "X-Microsoft-Antispam-Message-Info": "\n RC/585vrArbvxS5ckw3q5/BEGl5KYpZgyKLQcGOLNo7LPCeaDThss61/1bCci09z9rotUCgVZmuJ5Y6dYFvKcEhbfbGcN8TTbPB0pcDMoyMH99lytx9JwE7NeT28Zl4gbh+86rJuSgyBx75Wrgw97+j4iaoz6L/Vk1OiX/hnkIPSdAdnJpCMunE7pWecyI/YOYWqRHy/iJL0VAoD8kgitz8Jk77kz1mcjvNoXr8etyr6navZO+tldD+SYYffI9R8xLQN9VUKUjgYVMM1p6fcs2vW4nfMDO+eYm7t0UBp9RpxY+nECUf0bTu8J3BjPYLwTCa/lt8hpsQeD+WgiL+cbrnjNsG1yde6gQF5kWKawpZjO3/W2LAe9Bkt0T4vafth+x9wDfb1Cr1na6Ug6hNm4+IkTiN/aJeJ0QAa8Vna9yXnpYYgSjhGKbOGSPzFa1zku7mEb59dOumdcdpdfgk/QQJhi3QJgc9P2Ky2h7XrEUjrdp9X9dvj8iRraMdPLu7M32uHrgf3ptH6DdVfgje6bLXpF7jilmzQpVvEmfvxOH7zdD5ZeSeLpwHu1PUM7uTdayQbBVuCx+3JuKucLLbKv0eoY5w+aOnTJlsoE3UoepzzWZJu2n1feiz3t1vQYuZg21HhfmnYvr2ttkq+kqgrhXTdzcmBBsY7eEfVVusVMujATwWGciXudI9v2HlHh0oQMue8GH/XD1VY0iPD/cshvL13REY99u9VBh0xzoB0zCQ8irDIjrdDOufYkJTfaFsQ8KXN+cQrIeV7XH1RvMoOUxniRBHZJzAJbvW+Aj8VOkjEqTtDrb33NuQ+WIZz0EZSzEH4HZIAVW/AYnyB7E3Yl+4aMfqC6pl6P/3TXnCuNyuAy2vML4sVlKFBt78a0i3MNpaNYU3Mfjz+GvfJ7Mz7v+vvdQqHGelZN8IBthJj7LDdcNvNGqo29hj3z+H/QK/vIzHqcLDja/zpLo/xe9MdTlY4CrEfThNNybC9oU37x16sTxCrQoXdT7rXCyHRwk1Tk3PWuHRjdOqvBNqC8nFzdkvdeIYjCSVbtBN8MMqg0Ezu5D1zKE9cZdYEV08CZRd02ip4IMXksoWc16DSCCob3yir6s7cB/hxPo0Z8CyUvJmgFgY60FRbtDjnQ8G2ALLO5Ts1OcKm5WXSjXMOa0xgS5UURPnDUSeK3T+fjqyV4PLo/hgbxCmVXFDPBF0E8VwVbFzkuZ6V9roLsyZSbT6leZ9bRFMK1uTpNCokSHgpmDPILlMa6qj7sC99OOikqFkXsgdgQqu//fX0M164Ri66sSLKku83SRtYw7SmfbItvMydGuBeFlo97CoB43Fq2u6RpfrZbLeU5m4OjNMrNE8x5LM5Y9YRfWXQlIFtaLf4UxBx9dMue6jboCjbWuy93gwh/De6/VTSTOrEyNZg/rDDXkNXfewwzB0O60qUaTwDUyRWNadTeV0e5wOJ5Nakejn7GHJz5CUcsN9QiO9Ri/9HO4iD4BnFpHMNZwM9wuBgEuFXh3RTOspGkLxKNr3P6/RQG1TwMeEJKAKRDXwd+a+xxceRGKnWB+h1eTl6Em+/Y16QSuksVVktB295D4fC/BRMgzoTAz0x6ijLFaLMoeXDv1EgyhVW/rEPyYUkIrhspChzxVRJ3tAQSqMqnG3zEJRKa67vHdeRXetIZh4Zz32phg==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014)(13003099007);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n vdi4nxcYFR0QlXjledo7l98vtJ900GQ1NDn/p2YjUrBBWzvRBX3QyM+yAmBHQVZyr5jIlrY9PrNSpHYIcASs4EIZtxkdmxK40GCA341H6ZknwBondPstZwyuASD/q5y1YHdPZGZg7zF6gDhJ+TJW2h6EMvVnqAvIeXds06CC7GdDUUOJKibEWLt156Gjv7/wNF4UV6w4hUksdOIUavUghXA5E4Zr7scB9JDEmsLOGrHp3oMpSItejkY0EIVwvqIZ4VwLWJjETQFRddxXuS+wVzcsqp9yOI4xjKD9Y7hj9lAHF+OsS01Ei3qQnfP1HxWdCYipZvsRGqXAH48M3L/Z3Rp0pL7/yQZFcpFY03+l2b8hTaGYIlq+M55gf3RAnGJW8OVhxTDHOo+lTGY0+/RrwOPwCeCcBddJcJRYPe++B+UevR9egxtXNGxAGJTb0Uwh", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Feb 2026 08:50:00.0844 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 2983fc76-4156-4949-e0bf-08de6c6f33f9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n MWH0EPF000C6185.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ1PR12MB6220", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Ankit Agrawal <ankita@nvidia.com>\n\nThis series enables hugepfnmap support in QEMU for VFIO device memory\nregions that have non-power-of-2 sizes. This specifically addresses the\nneeds of Grace-based systems (GB200) where device memory is exposed\nas a BAR.\n\n## Problem\n\nOn Grace-based systems, device memory regions can have sizes like\n0x2F00F00000 (not power-of-2). The current QEMU VFIO mapping code\naligns each sparse mmap area independently using the trailing zeros\nof its size (ctz64), which results in suboptimal alignment for the\noverall VMA.\n\nThis prevents the kernel from using hugepfnmap that enables huge\npage mappings for device memory. Without proper alignment, the\nmapping falls back to PTE, significantly impacting performance\ndue to increased TLB pressure and page table overhead for large\nmemory regions.\n\n## Solution\n\nPatch 1: Sort sparse mmap regions by offset during setup and validate\n that they don't overlap. This ensures predictable mapping\n order and enables gap detection.\n\nPatch 2: Change the alignment strategy from per-sparse-region to\n whole-region alignment using pow2ceil(region->size). Create\n a single aligned base mapping for the entire region, then\n overlay sparse areas with MAP_FIXED. Gaps between sparse\n regions are explicitly unmapped.\n\nv3\n* New patch 2/3 to add Error **param in vfio_region_setup (Cedric)\n\nv2: https://lore.kernel.org/all/20260211030615.3202-1-ankita@nvidia.com/ [v2]\n* Fixed the code returning early without trace (Shameer, Alex)\n\nv1: https://lore.kernel.org/all/20260130040649.42485-1-ankita@nvidia.com/\n\nAnkit Agrawal (3):\n hw/vfio: sort and validate sparse mmap regions by offset\n vfio: Add Error ** parameter to vfio_region_setup()\n hw/vfio: align mmap to power-of-2 of region size for hugepfnmap\n\n hw/vfio/display.c | 2 +-\n hw/vfio/pci.c | 3 +-\n hw/vfio/region.c | 131 ++++++++++++++++++++++++++++++++----------\n hw/vfio/vfio-region.h | 2 +-\n 4 files changed, 105 insertions(+), 33 deletions(-)" }