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{ "id": 2196307, "url": "http://patchwork.ozlabs.org/api/covers/2196307/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/cover/20260213112717.1256823-1-aswin.murugan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260213112717.1256823-1-aswin.murugan@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-13T11:27:11", "name": "[v2,0/6] qcom: Add NVMEM bitfield support and reboot‑mode integration", "submitter": { "id": 90811, "url": "http://patchwork.ozlabs.org/api/people/90811/?format=api", "name": "Aswin Murugan", "email": "aswin.murugan@oss.qualcomm.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/cover/20260213112717.1256823-1-aswin.murugan@oss.qualcomm.com/mbox/", "series": [ { "id": 492084, "url": "http://patchwork.ozlabs.org/api/series/492084/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=492084", "date": "2026-02-13T11:27:11", "name": "qcom: Add NVMEM bitfield support and reboot‑mode integration", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492084/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2196307/comments/", "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=CPetq3fL;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=kQ1hzlOI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"CPetq3fL\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"kQ1hzlOI\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=aswin.murugan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fC8zS5vV8z1xr1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 13 Feb 2026 22:27:48 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 3B0E880FA1;\n\tFri, 13 Feb 2026 12:27:41 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 6D59083AA9; Fri, 13 Feb 2026 12:27:40 +0100 (CET)", "from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id A415B80B98\n for <u-boot@lists.denx.de>; Fri, 13 Feb 2026 12:27:37 +0100 (CET)", "from pps.filterd (m0279863.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 61D7bR471642029\n for <u-boot@lists.denx.de>; Fri, 13 Feb 2026 11:27:35 GMT", "from mail-pl1-f200.google.com (mail-pl1-f200.google.com\n [209.85.214.200])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4c9ptv2k1h-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Fri, 13 Feb 2026 11:27:35 +0000 (GMT)", "by mail-pl1-f200.google.com with SMTP id\n d9443c01a7336-2ab4de9580dso26479515ad.3\n for <u-boot@lists.denx.de>; Fri, 13 Feb 2026 03:27:35 -0800 (PST)", "from hu-aswinm-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-GUID": "eZBwqB1FYYaRqPX4rAGZJz6FDWAIiPeR", "X-Authority-Analysis": "v=2.4 cv=eaowvrEH c=1 sm=1 tr=0 ts=698f0aa7 cx=c_pps\n a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=5KLPUuaC_9wA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22\n a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=l-UPrZbCS1wS8v9bHbkA:9 a=QEXdDO2ut3YA:10\n a=uG9DUKGECoFWVXl0Dc02:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjEzMDA4NyBTYWx0ZWRfX1EhexV3DiGAV\n ofr+w7Hb2ckwrTlnhtTXDEabyqIjpl/OmmETz1DelWv/3qmBkkz1H7SjT18/OJZObXww9kRiZVT\n mPhtSk9kYCpEZbMIPDtr+mmA8kzHp/RePE43mWa/Tpeqr1jsyi4JbfqO2PEp+iitoQN3Is3yw44\n JxkAAwnvGRuP24r28/YkhsSTgCe+h88q67VxmXq/zKJ7qVTYDhRVpQW9WGjBbR6z18ATkvKo40a\n t9r9XGAjHYzMRbV3mQT3J4u+NOVau6l0WEc5KFQt9agOh5mCT4z91NARJPSmEw2sh2/nRN/K20k\n VQqIMqbtdTqfZJu5E75j67l7q2XdPTfm8ovWbiGXbvZFxCuzzPCsorFXavxDdIucW77nE/Aa5Kl\n sVLySWXPCHYcM12Y6799G5LLosZKLcwdfzsEmotUnm5ZmoRIFYsaIkWgFyVE1osiO1i4UFI8QcY\n 5WyN7X5Mnkjyuc3QQ8w==", "X-Proofpoint-ORIG-GUID": "eZBwqB1FYYaRqPX4rAGZJz6FDWAIiPeR", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-13_02,2026-02-12_03,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 adultscore=0\n lowpriorityscore=0 clxscore=1015 phishscore=0 impostorscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602130087", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "This patch series introduces bit-level granularity to NVMEM cells and\nadds complete reboot-mode support for Qualcomm platforms that store\nreboot reasons in PMIC registers.\n\nQualcomm SoCs rely on PMIC-backed reboot reason storage to implement\nfeatures like \"reboot bootloader\" for entering fastboot mode. However,\nthese PMIC registers often pack multiple fields into a single byte,\nrequiring fine-grained bit access that the current NVMEM subsystem does\nnot support.\n\nIn addition, PMIC generations differ in how reboot-related data is\nstored: older PMICs use PON (Power On) registers, while newer ones\nprovide SDAM regions. This series introduces a unified, NVMEM-based\napproach that works seamlessly across both architectures.\n\nThis version also integrates reboot-mode handling into Qualcomm board\ninitialization, enabling automatic fastboot entry when the reboot reason\nindicates bootloader mode.\n\nSigned-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>\n\n---\nChanges in v2:\n1. Replaced custom reboot reason handling with the standard U-Boot\n reboot-mode subsystem, per review feedback.\n2. Added bit-field support to the NVMEM core using the new \"bits\"\n property.\n3. Introduced the Qualcomm SPMI SDAM driver for unified PMIC storage\n access.\n4. Updated the reboot-mode driver to support variable-sized NVMEM cells.\n5. Added device tree configuration for the QCS615 RIDE board.\n6. Enabled reboot-mode in qcom_defconfig.\n7. Integrated reboot-mode detection into Snapdragon board\n initialization:\n - Added qcom_handle_reboot_mode() in board_late_init() to enable\n automatic fastboot entry on \"reboot bootloader\".\n\nLink to v1:\nhttps://lore.kernel.org/all/20260108065533.1143179-1-aswin.murugan@oss.qualcomm.com/\n---\n\nAswin Murugan (6):\n reboot-mode: Use actual cell size instead of sizeof(u32)\n misc: Add support for bit fields in NVMEM cells\n misc: qcom: Add Qualcomm SPMI SDAM NVMEM driver\n mach-snapdragon: Integrate reboot-mode handling\n dts: qcs615-ride-u-boot.dtsi: Add reboot-mode support\n qcom_defconfig: Enable reboot-mode support in qcom_defconfig\n\n arch/arm/dts/qcs615-ride-u-boot.dtsi | 26 +++\n arch/arm/mach-snapdragon/board.c | 56 ++++--\n configs/qcom_defconfig | 3 +\n drivers/misc/Kconfig | 8 +\n drivers/misc/Makefile | 1 +\n drivers/misc/nvmem.c | 241 ++++++++++++++++++++++--\n drivers/misc/qcom-spmi-sdam.c | 200 ++++++++++++++++++++\n drivers/reboot-mode/reboot-mode-nvmem.c | 5 +-\n include/nvmem.h | 4 +\n 9 files changed, 517 insertions(+), 27 deletions(-)\n create mode 100644 drivers/misc/qcom-spmi-sdam.c" }