Cover Letter Detail
Show a cover letter.
GET /api/covers/2196220/?format=api
{ "id": 2196220, "url": "http://patchwork.ozlabs.org/api/covers/2196220/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/cover/20260213055342.3124872-1-anup.patel@oss.qualcomm.com/", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "https://github.com/riscv/opensbi/commit/{}" }, "msgid": "<20260213055342.3124872-1-anup.patel@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-13T05:53:34", "name": "[v2,0/8] Extend irqchip framework for M-mode interrupts", "submitter": { "id": 92322, "url": "http://patchwork.ozlabs.org/api/people/92322/?format=api", "name": "Anup Patel", "email": "anup.patel@oss.qualcomm.com" }, "mbox": "http://patchwork.ozlabs.org/project/opensbi/cover/20260213055342.3124872-1-anup.patel@oss.qualcomm.com/mbox/", "series": [ { "id": 492060, "url": "http://patchwork.ozlabs.org/api/series/492060/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/list/?series=492060", "date": "2026-02-13T05:53:41", "name": "Extend irqchip framework for M-mode interrupts", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492060/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2196220/comments/", "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=ohBRpYcZ;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=otf1f0LD;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org;\n envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fC1bR1YSzz1xpl\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 13 Feb 2026 16:54:59 +1100 (AEDT)", "from localhost ([::1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1vqm8j-000000032PK-1LJ7;\n\tFri, 13 Feb 2026 05:54:53 +0000", "from mx0a-0031df01.pphosted.com ([205.220.168.131])\n\tby bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1vqm8g-000000032Nb-2zqV\n\tfor opensbi@lists.infradead.org;\n\tFri, 13 Feb 2026 05:54:52 +0000", "from pps.filterd (m0279865.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 61CLKEFK1067977;\n\tFri, 13 Feb 2026 05:53:47 GMT", "from apblrppmta02.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4c9d09kruh-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tFri, 13 Feb 2026 05:53:47 +0000 (GMT)", "from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1])\n\tby APBLRPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id\n 61D5rh60006111;\n\tFri, 13 Feb 2026 05:53:43 GMT", "from pps.reinject (localhost [127.0.0.1])\n\tby APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4c5xfn97kg-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tFri, 13 Feb 2026 05:53:43 +0000", "from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com\n [127.0.0.1])\n\tby pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 61D5rhjr006085;\n\tFri, 13 Feb 2026 05:53:43 GMT", "from hu-devc-blr-u24-a.qualcomm.com (hu-anuppate-blr.qualcomm.com\n [10.131.36.165])\n\tby APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 61D5rhTT006082\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n\tFri, 13 Feb 2026 05:53:43 +0000", "by hu-devc-blr-u24-a.qualcomm.com (Postfix, from userid 486687)\n\tid C5830235AE; Fri, 13 Feb 2026 11:23:42 +0530 (+0530)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:Cc\n\t:To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:\n\tResent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:\n\tList-Owner; bh=NUrA+624XuGhmI2Gi63tiwIjFVZoFBtoKWxe6MrYGhA=; b=ohBRpYcZXr7XBf\n\t9jQQTgR7Ke3amqT7+n3Ub7+x2t5nARWynqhW0sZ3PtXhFfBLiVG0tyjXwrkda3dg+DUCzpxWbr/lh\n\ta881Kab3vQTkiKOlFX0n9MypWQwC/AhmIyZzZPnqWCeFLw/qQ1EniZCumAB1UFZqYsJarfybXDn0Y\n\t1vBmKZci3/BRNguz9HfeeKnIC09pt4Sc2TfktFqthIB/swEOJ5EFyccRD1M4V+Loumr/bEXuyr2KF\n\t92WbozdmMpUk3UV2Qb9akDcr5mrILAr96uSod0w8Rs2MGMdhVKgR1bDMkPCZFyY4J8X2mNUtkbHCO\n\tBDbPawbSM6dEU8EmEDgw==;", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:date:from:message-id:mime-version\n\t:subject:to; s=qcppdkim1; bh=c+3AVzc1Q2iAI1er1MJQK3MPeC7Uprp2dt2\n\trNzCmWNc=; b=otf1f0LDpWtqj5swTxtjGiQ9/EdbWjJK4c2cQey6UPunV7S70Er\n\txlodilXYYqKbWcNzFAv/tiv6s1mLvGzfw9bVhoxV0eU8942O4TUVD+6iNN7ssrY4\n\twb6yk5q2WvYN1z3GJZAyZQZILaWITh/Xn/AxZUWSgzGzAyEANAcfNjP2NF/R+OBf\n\t93Hb5Go4c6Sqf0sSn8+TGSZka4ubVmyWS159I7hGxP3rdHX7TkMdQ+wP94alLNfP\n\t6uw9gQ/meHfTEe46AdIPU82ppkathZu+5VUm0GUldPsqkEKcFURAjMq63D8yZpNW\n\tC3xOMJ1SdMRR8Fz/YNDBO8lPZhPH1RHfJyA==" ], "From": "Anup Patel <anup.patel@oss.qualcomm.com>", "To": "Atish Patra <atish.patra@linux.dev>", "Cc": "Andrew Jones <andrew.jones@oss.qualcomm.com>,\n Raymond Mao <raymond.mao@riscstar.com>,\n Dave Patel <dave.patel@riscstar.com>,\n Samuel Holland <samuel.holland@sifive.com>,\n Anup Patel <anup@brainfault.org>, opensbi@lists.infradead.org,\n Anup Patel <anup.patel@oss.qualcomm.com>", "Subject": "[PATCH v2 0/8] Extend irqchip framework for M-mode interrupts", "Date": "Fri, 13 Feb 2026 11:23:34 +0530", "Message-ID": "<20260213055342.3124872-1-anup.patel@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.43.0", "MIME-Version": "1.0", "X-QCInternal": [ "smtphost", "smtphost" ], "X-Proofpoint-Virus-Version": [ "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-12_05,2026-02-12_03,2025-10-01_01" ], "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjEzMDA0MiBTYWx0ZWRfXwM3C53lmL6Oc\n WQRvycRoaboVdEdlBc6yqqJimPd/vWGORAkqeWCpqyb9qg62JXs7l/K5J4vkZkC7mf/+doayp3i\n iKTuGmOyCKwKStAZc7NO1IPbs3JNYz8VR2LVwPFIa6IA1DIpab6N3nKAiFKWZQIIzrL/2VTRZDq\n cIq9tR2L+I6EbyAErLyqwJaBgsGTVjzjrHGclPEXJQJ9MoLyELfTw53Oml2KuI3v/oVfeyGcxMo\n yqaCK4ZgWiY77TuQ91/v1tVro0ogiCivmFD3Kv9bIKFRavkxeDYmycS7NAh+fE18cmEZ3G6YRhM\n Ti69q6Y+VUmF7QE5jRfzEfY8fuaL97HVKHr+ZUD7aHwbE+cY9/HtOh2zX2xqTmeKoFmgUmmC20l\n m8dVFpfe7KcpD1GQL8dPxKG5rlQeJVUC2MyWcKNQzKgzzA1pS/8ZqiSgodO3kdMoDP5FlzAWuR1\n DWWyDHz2jNQAHCpDQnQ==", "X-Proofpoint-GUID": "0CgT_ScA-Wl_dt5nT2qM7ssihSQlpa-c", "X-Authority-Analysis": "v=2.4 cv=Y6j1cxeN c=1 sm=1 tr=0 ts=698ebc6b cx=c_pps\n a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=HzLeVaNsDn8A:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22\n a=GgsMoib0sEa3-_RKJdDe:22 a=NEAV23lmAAAA:8 a=8fTsYDokL4cmS8J0QHoA:9", "X-Proofpoint-ORIG-GUID": "0CgT_ScA-Wl_dt5nT2qM7ssihSQlpa-c", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 malwarescore=0 adultscore=0 suspectscore=0 bulkscore=0\n lowpriorityscore=0 phishscore=0 priorityscore=1501 impostorscore=0\n clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2602130042", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20260212_215450_758553_F5138803 ", "X-CRM114-Status": "GOOD ( 10.07 )", "X-Spam-Score": "-2.7 (--)", "X-Spam-Report": "Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: To handle interrupts in M-mode,\n the OpenSBI irqchip framework\n needs to support: 1) Multiple interrupt controllers where each targets a\n subset of harts 2) Hierarchical interrupt controllers (e.g. APLIC [...]\n Content analysis details: (-2.7 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low\n trust\n [205.220.168.131 listed in list.dnswl.org]\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n 0.0 RCVD_IN_VALIDITY_CERTIFIED_BLOCKED RBL: ADMINISTRATOR NOTICE: The\n query to Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [205.220.168.131 listed in\n sa-trusted.bondedsender.org]\n 0.0 RCVD_IN_VALIDITY_SAFE_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to\n Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [205.220.168.131 listed in\n sa-accredit.habeas.com]\n 0.0 RCVD_IN_VALIDITY_RPBL_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to\n Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [205.220.168.131 listed in\n bl.score.senderscore.com]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "To handle interrupts in M-mode, the OpenSBI irqchip framework\nneeds to support:\n1) Multiple interrupt controllers where each targets a\n subset of harts\n2) Hierarchical interrupt controllers (e.g. APLIC + IMSIC)\n3) Registering handler for hardware interrupt of a\n particular interrupt controller out of multiple\n multiple interrupt controllers\n\nThe needs to be achieved without over-consuming memory.\n\nThese patches can also be found in irqchip_imp_v2 branch\nat: https://github.com/avpatel/opensbi.git\n\nChanges since v1:\n - Fixed typos in PATCH4 and PATCH5\n - Improved sbi_irqchip_process() and sbi_irqchip_add_device()\n based on Samuel's suggestion\n\nAnup Patel (8):\n lib: sbi_irqchip: Use chip as variable name for irqchip device\n lib: sbi_irqchip: Rename irq_handle() callback to process_hwirqs()\n lib: utils/irqchip: Fix context_map init in\n irqchip_plic_update_context_map()\n lib: utils/irqchip: Add IDC to hartindex map in struct aplic_data\n lib: sbi_irqchip: Support irqchip device targetting subset of harts\n lib: utils/irqchip: Add unique_id to plic, aplic, and imsic data\n lib: sbi_irqchip: Associate 32-bit unique ID for each irqchip device\n lib: sbi_irqchip: Allow registering interrupt handlers\n\n include/sbi/sbi_irqchip.h | 74 +++++-\n include/sbi_utils/irqchip/aplic.h | 2 +\n include/sbi_utils/irqchip/imsic.h | 1 +\n include/sbi_utils/irqchip/plic.h | 1 +\n lib/sbi/sbi_irqchip.c | 281 +++++++++++++++++++++--\n lib/utils/fdt/fdt_helper.c | 3 +\n lib/utils/irqchip/aplic.c | 14 +-\n lib/utils/irqchip/fdt_irqchip_aplic.c | 54 ++++-\n lib/utils/irqchip/fdt_irqchip_plic.c | 5 +\n lib/utils/irqchip/imsic.c | 19 +-\n lib/utils/irqchip/plic.c | 7 +-\n platform/generic/openhwgroup/ariane.c | 1 +\n platform/generic/openhwgroup/openpiton.c | 1 +\n platform/kendryte/k210/platform.c | 1 +\n platform/nuclei/ux600/platform.c | 1 +\n platform/template/platform.c | 1 +\n 16 files changed, 437 insertions(+), 29 deletions(-)" }