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{ "id": 2195891, "url": "http://patchwork.ozlabs.org/api/covers/2195891/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/cover/20260212091326.2240990-1-linopeng@andestech.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260212091326.2240990-1-linopeng@andestech.com>", "list_archive_url": null, "date": "2026-02-12T09:13:18", "name": "[0/8] *** Add RISC-V zvfofp8min intrinsic ***", "submitter": { "id": 92634, "url": "http://patchwork.ozlabs.org/api/people/92634/?format=api", "name": "Lino Hsing-Yu Peng", "email": "linopeng@andestech.com" }, "mbox": "http://patchwork.ozlabs.org/project/gcc/cover/20260212091326.2240990-1-linopeng@andestech.com/mbox/", "series": [ { "id": 491947, "url": "http://patchwork.ozlabs.org/api/series/491947/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=491947", "date": "2026-02-12T09:13:18", "name": "*** Add RISC-V zvfofp8min intrinsic ***", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491947/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2195891/comments/", "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n 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ESMTPS id 0E94E4BA2E16\n for <gcc-patches@gcc.gnu.org>; Thu, 12 Feb 2026 09:22:59 +0000 (GMT)", "from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134])\n by Atcsqr.andestech.com with ESMTP id 61C9MqKh011415;\n Thu, 12 Feb 2026 17:22:52 +0800 (+08)\n (envelope-from linopeng@andestech.com)", "from atccpl01.andestech.com (10.0.15.149) by ATCPCS34.andestech.com\n (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 12 Feb\n 2026 17:22:52 +0800" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 3F7144BA23F1", "OpenDKIM Filter v2.11.0 sourceware.org 0E94E4BA2E16" ], "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 0E94E4BA2E16", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1770888180; cv=none;\n b=pWn7G7/7ClhypUt91Ne+QZxO73d8mgrZ68MMvyxMt3zI+AHPh6Gy8PNgyfWSuA2I8u11bgzTyCg+eOHiwr86Fw4tWUBNcY24p/cSBPDpp6Df4ZgSyGCGjXVRCRAdwDrDV+qw/7QaPtxcl/aTWsrcyI1niOBbRjstqDJzZ/OoXt0=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1770888180; c=relaxed/simple;\n bh=1vuph+VpOsrz83wcbBTinC1ysFq+CKrWIQFlcdPjiuo=;\n h=From:To:Subject:Date:Message-ID:MIME-Version;\n b=ic47MEQ4Y9L8ksdaqvFsTOIq9iuhOwRSU0hWjbpTJ06Zs8lIBgxyCg068BlBUte119QkKvxwpoaJQ7LYGpEjdgP7DK0Jc1riU10xWpy+FSfOmCKNyZxZjfh81eVtxPqXLVbwNwhxwbQEBvWnSWcDXFVu9TyVAhbbsYTeUUYgLCM=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Lino Hsing-Yu Peng <linopeng@andestech.com>", "To": "<gcc-patches@gcc.gnu.org>", "CC": "Lino Hsing-Yu Peng <linopeng1019@gmail.com>", "Subject": "[PATCH 0/8] *** Add RISC-V zvfofp8min intrinsic ***", "Date": "Thu, 12 Feb 2026 17:13:18 +0800", "Message-ID": "<20260212091326.2240990-1-linopeng@andestech.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.0.15.149]", "X-ClientProxiedBy": "ATCPCS33.andestech.com (10.0.1.100) To\n ATCPCS34.andestech.com (10.0.1.134)", "X-DKIM-Results": "atcpcs34.andestech.com; dkim=none;", "X-DNSRBL": "", "X-MAIL": "Atcsqr.andestech.com 61C9MqKh011415", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Lino Hsing-Yu Peng <linopeng1019@gmail.com>\n\nThis series adds initial GCC support for the RISC-V Zvfofp8min extension.\n\nIt first introduces Zvfofp8min ISA extension support, then adds FP8 conversion\nsupport in RVV builtins and machine descriptions (FP8<->BF16 and FP32->FP8),\nand updates vsetvl handling so altfmt requirements are propagated from\ninstruction patterns through vsetvl generation and the vsetvl pass.\n\nThe final patch adds testsuite coverage under gcc.target/riscv/rvv, including\npolicy/non-policy and overloaded/non-overloaded variants for vfncvt,\nvfncvtbf16, and vfwcvtbf16, plus an altfmt interleave test.\n\nLino Hsing-Yu Peng (8):\n RISC-V: Add zvfofp8min ISA extension support\n RISC-V: Add zvfofp8min FP8 to BF16 vector conversions\n RISC-V: Add zvfofp8min BF16 to FP8 narrowing conversions\n RISC-V: Add zvfofp8min FP32 to FP8 narrowing conversions\n RISC-V: Plumb altfmt through vsetvl patterns\n RISC-V: Mark zvfofp8min altfmt on insns\n RISC-V: Track altfmt in vsetvl pass\n RISC-V: Add zvfofp8min tests\n\n gcc/common/config/riscv/riscv-common.cc | 2 +\n gcc/config/riscv/genrvv-type-indexer.cc | 10 +\n gcc/config/riscv/riscv-ext.def | 13 +\n gcc/config/riscv/riscv-ext.opt | 3 +-\n gcc/config/riscv/riscv-v.cc | 8 +-\n .../riscv/riscv-vector-builtins-bases.cc | 118 ++-\n .../riscv/riscv-vector-builtins-bases.h | 3 +\n .../riscv/riscv-vector-builtins-functions.def | 23 +\n .../riscv/riscv-vector-builtins-shapes.cc | 191 ++++-\n .../riscv/riscv-vector-builtins-shapes.h | 7 +\n .../riscv/riscv-vector-builtins-types.def | 14 +\n gcc/config/riscv/riscv-vector-builtins.cc | 63 +-\n gcc/config/riscv/riscv-vector-builtins.def | 8 +-\n gcc/config/riscv/riscv-vector-builtins.h | 7 +\n gcc/config/riscv/riscv-vsetvl.cc | 189 ++++-\n gcc/config/riscv/riscv-vsetvl.def | 15 +\n gcc/config/riscv/riscv.md | 6 +\n gcc/config/riscv/vector-float8.md | 154 ++++\n gcc/config/riscv/vector.md | 74 +-\n gcc/doc/riscv-ext.texi | 4 +\n gcc/testsuite/gcc.target/riscv/arch-61.c | 5 +\n .../rvv/base/zvfofp8min-altfmt-interleave.c | 59 ++\n gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 3 +\n .../non-policy/non-overloaded/riscv_vector.h | 11 +\n .../non-policy/non-overloaded/vfncvt.c | 326 ++++++++\n .../non-policy/non-overloaded/vfncvtbf16.c | 390 +++++++++\n .../non-policy/non-overloaded/vfwcvtbf16.c | 102 +++\n .../non-policy/overloaded/riscv_vector.h | 11 +\n .../zvfofp8min/non-policy/overloaded/vfncvt.c | 326 ++++++++\n .../non-policy/overloaded/vfncvtbf16.c | 390 +++++++++\n .../non-policy/overloaded/vfwcvtbf16.c | 102 +++\n .../policy/non-overloaded/riscv_vector.h | 11 +\n .../zvfofp8min/policy/non-overloaded/vfncvt.c | 646 +++++++++++++++\n .../policy/non-overloaded/vfncvtbf16.c | 774 ++++++++++++++++++\n .../policy/non-overloaded/vfwcvtbf16.c | 198 +++++\n .../policy/overloaded/riscv_vector.h | 11 +\n .../rvv/zvfofp8min/policy/overloaded/vfncvt.c | 646 +++++++++++++++\n .../zvfofp8min/policy/overloaded/vfncvtbf16.c | 774 ++++++++++++++++++\n .../zvfofp8min/policy/overloaded/vfwcvtbf16.c | 198 +++++\n 39 files changed, 5818 insertions(+), 77 deletions(-)\n create mode 100644 gcc/config/riscv/vector-float8.md\n create mode 100644 gcc/testsuite/gcc.target/riscv/arch-61.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfofp8min-altfmt-interleave.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/non-overloaded/riscv_vector.h\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/non-overloaded/vfncvt.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/non-overloaded/vfncvtbf16.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/non-overloaded/vfwcvtbf16.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/overloaded/riscv_vector.h\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/overloaded/vfncvt.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/overloaded/vfncvtbf16.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/non-policy/overloaded/vfwcvtbf16.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/non-overloaded/riscv_vector.h\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/non-overloaded/vfncvt.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/non-overloaded/vfncvtbf16.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/non-overloaded/vfwcvtbf16.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/overloaded/riscv_vector.h\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/overloaded/vfncvt.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/overloaded/vfncvtbf16.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/zvfofp8min/policy/overloaded/vfwcvtbf16.c" }