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{ "id": 2195003, "url": "http://patchwork.ozlabs.org/api/covers/2195003/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260210113041.138430-1-john.madieu.xa@bp.renesas.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "list_archive_url": null, "date": "2026-02-10T11:30:24", "name": "[v5,00/16] PCI: renesas: Add RZ/G3E PCIe controller support", "submitter": { "id": 89876, "url": "http://patchwork.ozlabs.org/api/people/89876/?format=api", "name": "John Madieu", "email": "john.madieu.xa@bp.renesas.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/cover/20260210113041.138430-1-john.madieu.xa@bp.renesas.com/mbox/", "series": [ { "id": 491658, "url": "http://patchwork.ozlabs.org/api/series/491658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=491658", "date": "2026-02-10T11:30:24", "name": "PCI: renesas: Add RZ/G3E PCIe controller support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/491658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2195003/comments/", "headers": { "Return-Path": "\n <linux-pci+bounces-47067-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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10 Feb 2026 20:32:09 +0900", "from ubuntu.adwin.renesas.com (unknown [10.226.92.55])\n\tby relmlir6.idc.renesas.com (Postfix) with ESMTP id 5070241A118C;\n\tTue, 10 Feb 2026 20:32:03 +0900 (JST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1770723138; cv=none;\n b=fuMxU/YqKHfXY6DS8M11ev4ZdXbG9wN6olJ7/Xa0UPSLzdlpnt67RnaRoCjWUovh7s6Ehjm70dbMc2cWp6Spc55UUfEs2ICjVCEmPg9tJgJJQh4qY/EXoOVZ/llkwXi8PUtz171rkpzdlu/jwR5i5PUhaVTnr5+ywKIMLRXwRE8=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1770723138; c=relaxed/simple;\n\tbh=r6+7M6tmZKJkU+SaH7YLVv9ouxUqs6tvKf40WWRrTVo=;\n\th=From:To:Cc:Subject:Date:Message-ID:MIME-Version;\n b=PsSpB7GMH9Ys0NUqr9P0fJN595bhz/gMPoM+QnpcJMEwW88Fb55CREYEY+Bn0GY/CsMkfsQfqiUFbzV+M3iyZXA4IliXRZyBrGYGx1C0RUVS3N1X6agaH8+P/FiQfJksUzVBlZFkzBZ7nc0S7QeqwC+HmVlhoyTsQjKz2Qgdqow=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=bp.renesas.com;\n spf=pass smtp.mailfrom=bp.renesas.com;\n arc=none smtp.client-ip=210.160.252.172", "X-CSE-ConnectionGUID": "LhpKC8NHRg6Z9U7kClAG3Q==", "X-CSE-MsgGUID": "0WCdJohqS5u533TOPsrvmg==", "From": "John Madieu <john.madieu.xa@bp.renesas.com>", "To": "claudiu.beznea.uj@bp.renesas.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tgeert+renesas@glider.be,\n\tkrzk+dt@kernel.org", "Cc": "robh@kernel.org,\n\tbhelgaas@google.com,\n\tconor+dt@kernel.org,\n\tmagnus.damm@gmail.com,\n\tbiju.das.jz@bp.renesas.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-clk@vger.kernel.org,\n\tjohn.madieu@gmail.com,\n\tJohn Madieu <john.madieu.xa@bp.renesas.com>", "Subject": "[PATCH v5 00/16] PCI: renesas: Add RZ/G3E PCIe controller support", "Date": "Tue, 10 Feb 2026 12:30:24 +0100", "Message-ID": "<20260210113041.138430-1-john.madieu.xa@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with\nthe existing RZ/G3S PCIe controller, but with several key differences.\nThis series adds support for the RZ/G3E PCIe controller by extending the existing\nRZ/G3S driver and device tree bindings.\n\nKey differences between RZ/G3E and RZ/G3S PCIe controllers:\n\nLink Speed Support:\n - RZ/G3E: Supports PCIe Gen3 (8.0 GT/s) alongside Gen2 (5.0 GT/s)\n - RZ/G3S: Supports PCIe Gen2 (5.0 GT/s) only\n\nReset Control:\n - RZ/G3E: Uses register-based reset control mechanism\n - RZ/G3S: Uses exclusively external reset control signals\n\nInbound Window Configuration:\n - RZ/G3E: Requires precise power-of-2 window coverage with strict address\n alignment constraints. Non-power-of-2 memory regions must be split into\n multiple windows to avoid over-mapping, ensuring proper hardware address\n decoding for DMA operations.\n - RZ/G3S: Uses a simpler approach that rounds up to the next power-of-2,\n creating single larger windows. The hardware tolerates over-mapped regions.\n\nClass/Revision IDs:\n - RZ/G3E: Requires explicit setting of class/revision values\n - RZ/G3S: Has default values in hardware\n\nClock Naming:\n - RZ/G3E: Uses \"clkpmu\" clock for power management\n - RZ/G3S: Uses \"clkl1pm\" PM control clock while CLKREQ_B is deasserting\n\nPhy Settings:\n - RZ/G3E: Does not need PHY settings as it works with default hw values\n - RZ/G3S: Requires explicit PHY settings\n\nThis series extends the existing driver to detect the SoC type from the device\ntree compatible string and configure the controller appropriately. The updates\nare minimal and focused on the hardware-specific differences while keeping the\ncommon code paths unified.\n\nChanges:\n\nv5:\n - Introduced new patch to reorder reset handling\n - Introduced rzg3s_sysc_config() helper to handle SYS config\n - Collected Tags on documentation\n\nv4:\n - Collected Ab tag\n - Fixed binding clock name constraint\n\nv3:\n - Removed extra MaxItems in binding causing warnings\n - Fix potential crash for non-initialized rcdev in CPG driver\n - Fix binding contraints replacing 'description' with 'const' as per\n Geert and Rob's comment\n\nv2:\n - Address Bjorn typo comments\n - Address Claidiu's comment on stylish\n - Use single inbound-window-configuration function for both G3E/G3S\n - Refactor goto laballing as per Claudiu's comments\n - Update bindings and reused G3S's interrupt ordering\n * This involves reordering interrupts in dt\n - Remove Board-specific PCIe dma-range.\n\n\nJohn Madieu (16):\n PCI: rzg3s-host: Fix reset handling in probe error path\n PCI: renesas: rzg3s: Rework inbound window algorithm for multi-SoC\n support\n clk: renesas: rzv2h-cpg: Add support for init_{off|asserted}\n clocks/resets\n clk: renesas: r9a09g047: Add PCIe clocks and reset\n dt-bindings: PCI: renesas,r9a08g045s33-pcie: Fix naming properties\n dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC\n PCI: rzg3s-host: Make SYSC register offsets SoC-specific\n PCI: rzg3s-host: Make configuration reset lines optional\n PCI: rzg3s-host: Reorder reset assertion during suspend\n PCI: rzg3s-host: Add SoC-specific configuration and initialization\n callbacks\n PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility\n PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support\n PCI: rzg3s-host: Add support for RZ/G3E PCIe controller\n arm64: dts: renesas: r9a09g047: Add PCIe node\n arm64: dts: renesas: r9a09g047e57-smarc-som: Add PCIe reference clock\n arm64: dts: renesas: r9a09g047e57-smarc: Enable PCIe\n\n .../bindings/pci/renesas,r9a08g045-pcie.yaml | 121 ++++--\n arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 69 ++++\n .../boot/dts/renesas/r9a09g047e57-smarc.dts | 16 +\n .../boot/dts/renesas/renesas-smarc2.dtsi | 4 +\n .../boot/dts/renesas/rzg3e-smarc-som.dtsi | 11 +\n drivers/clk/renesas/r9a09g047-cpg.c | 5 +\n drivers/clk/renesas/rzv2h-cpg.c | 24 +-\n drivers/clk/renesas/rzv2h-cpg.h | 34 +-\n drivers/pci/controller/pcie-rzg3s-host.c | 373 ++++++++++++++----\n 9 files changed, 538 insertions(+), 119 deletions(-)" }