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{
    "id": 2194996,
    "url": "http://patchwork.ozlabs.org/api/covers/2194996/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260210-phys_addr-v4-0-725a589e83c8@rev.ng/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
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    "msgid": "<20260210-phys_addr-v4-0-725a589e83c8@rev.ng>",
    "list_archive_url": null,
    "date": "2026-02-10T11:33:11",
    "name": "[v4,0/8] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS",
    "submitter": {
        "id": 92408,
        "url": "http://patchwork.ozlabs.org/api/people/92408/?format=api",
        "name": "Anton Johansson",
        "email": "anjo@rev.ng"
    },
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260210-phys_addr-v4-0-725a589e83c8@rev.ng/mbox/",
    "series": [
        {
            "id": 491656,
            "url": "http://patchwork.ozlabs.org/api/series/491656/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=491656",
            "date": "2026-02-10T11:33:12",
            "name": "single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS",
            "version": 4,
            "mbox": "http://patchwork.ozlabs.org/series/491656/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/covers/2194996/comments/",
    "headers": {
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        ],
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        "Subject": "[PATCH v4 0/8] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS",
        "Date": "Tue, 10 Feb 2026 12:33:11 +0100",
        "Message-Id": "<20260210-phys_addr-v4-0-725a589e83c8@rev.ng>",
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        "X-Change-ID": "20251104-phys_addr-b0f47ea3014a",
        "To": "qemu-devel@nongnu.org",
        "Cc": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n  Richard Henderson <richard.henderson@linaro.org>,\n  Anton Johansson <anjo@rev.ng>, palmer@dabbelt.com, alistair.francis@wdc.com,\n  pbonzini@redhat.com, gaosong@loongson.cn, maobibo@loongson.cn,\n  deller@gmx.de, Brian Cain <brian.cain@oss.qualcomm.com>",
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        "X-Spam_bar": "--",
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        "Reply-to": "Anton Johansson <anjo@rev.ng>",
        "From": "Anton Johansson via qemu development <qemu-devel@nongnu.org>",
        "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org",
        "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"
    },
    "content": "The target macro TARGET_PHYS_ADDR_SPACE_BITS is unused since commit\n\n  2e8fe327eb6 (\"accel/tcg: Simplify L1_MAP_ADDR_SPACE_BITS\"),\n\nreplace the handful of remaining uses with runtime functions or\nconstants.\n\nFor discussion see:\n\n  https://lore.kernel.org/qemu-devel/8f0db5c1-f20b-4b7a-8d6c-76ce7ec7b4e0@linaro.org/\n\nSuggested-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Anton Johansson <anjo@rev.ng>\n---\nChanges in v4:\n- Revert to using 40 bit physical addresses for HPPA to not break SeaBIOS\n  functional tests. This will be addressed in a separate series.\n- Added HPPA patch 3/8 to convert a missed 32-bit abs -> physical\n  address conversion.\n- Link to v3: https://lore.kernel.org/qemu-devel/20260112-phys_addr-v3-0-5f90fdb4015f@rev.ng\n\nChanges in v3:\n- Added reviewed-by;\n- Widened CC;\n- Link to v2: https://lore.kernel.org/qemu-devel/20251215-phys_addr-v2-0-633aa1d922cd@rev.ng\n\nChanges in v2:\n- Move alpha_phys_addr_space_bits() to linux-user/alpha/target_proc.h\n  (Richard);\n- Link to v1: https://lore.kernel.org/qemu-devel/20251209-phys_addr-v1-0-c387f3e72d77@rev.ng\n\n---\nAnton Johansson (8):\n      target/alpha: Introduce alpha_phys_addr_space_bits()\n      target/hppa: Define PA[20|1X] physical address space size\n      hw/hppa: Use hppa_abs_to_phys_pa1x()\n      target/i386: Drop physical address range checks\n      target/loongarch: Introduce loongarch_palen_mask()\n      hw/loongarch: Use loongarch_palen_mask()\n      hw/riscv: Fix IOMMU PAS capability to 56 bits\n      Drop TARGET_PHYS_ADDR_SPACE_BITS\n\n include/exec/cpu-defs.h           |  3 ---\n include/exec/poison.h             |  2 --\n include/hw/loongarch/boot.h       |  3 ++-\n linux-user/alpha/target_proc.h    |  1 +\n target/alpha/cpu-param.h          |  3 ---\n target/arm/cpu-param.h            |  2 --\n target/avr/cpu-param.h            |  1 -\n target/hexagon/cpu-param.h        |  1 -\n target/hppa/cpu-param.h           |  3 ---\n target/hppa/cpu.h                 |  1 +\n target/i386/cpu-param.h           |  2 --\n target/i386/tcg/helper-tcg.h      |  2 --\n target/loongarch/cpu-mmu.h        |  1 +\n target/loongarch/cpu-param.h      |  1 -\n target/loongarch/internals.h      |  1 -\n target/m68k/cpu-param.h           |  1 -\n target/microblaze/cpu-param.h     |  2 --\n target/mips/cpu-param.h           |  2 --\n target/openrisc/cpu-param.h       |  1 -\n target/ppc/cpu-param.h            |  7 -------\n target/riscv/cpu-param.h          |  2 --\n target/rx/cpu-param.h             |  1 -\n target/s390x/cpu-param.h          |  1 -\n target/sh4/cpu-param.h            |  1 -\n target/sparc/cpu-param.h          |  2 --\n target/tricore/cpu-param.h        |  1 -\n target/xtensa/cpu-param.h         |  1 -\n hw/hppa/machine.c                 |  2 +-\n hw/loongarch/boot.c               | 28 ++++++++++++++++------------\n hw/loongarch/virt.c               |  5 ++++-\n hw/riscv/riscv-iommu.c            | 12 +++++++++---\n target/hppa/mem_helper.c          | 32 +++++++++++++++++++++++++++-----\n target/i386/cpu.c                 |  9 +++------\n target/i386/kvm/kvm.c             |  3 +--\n target/loongarch/cpu_helper.c     | 14 +++++++++++---\n target/loongarch/tcg/tlb_helper.c | 12 ++++++++----\n 36 files changed, 85 insertions(+), 81 deletions(-)"
}