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{ "id": 2194421, "url": "http://patchwork.ozlabs.org/api/covers/2194421/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/cover/20260208220454.51741-1-zihong.plct@isrc.iscas.ac.cn/", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260208220454.51741-1-zihong.plct@isrc.iscas.ac.cn>", "list_archive_url": null, "date": "2026-02-08T22:04:35", "name": "[RFC,0/5] riscv: Add libmvec routines", "submitter": { "id": 91553, "url": "http://patchwork.ozlabs.org/api/people/91553/?format=api", "name": "Yao Zihong", "email": "zihong.plct@isrc.iscas.ac.cn" }, "mbox": "http://patchwork.ozlabs.org/project/glibc/cover/20260208220454.51741-1-zihong.plct@isrc.iscas.ac.cn/mbox/", "series": [ { "id": 491443, "url": "http://patchwork.ozlabs.org/api/series/491443/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=491443", "date": "2026-02-08T22:04:40", "name": "riscv: Add libmvec routines", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/491443/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2194421/comments/", "headers": { "Return-Path": "<libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "libc-alpha@sourceware.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "libc-alpha@sourceware.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=2620:52:6:3111::32; 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server2.sourceware.org", "From": "Yao Zihong <zihong.plct@isrc.iscas.ac.cn>", "To": "libc-alpha@sourceware.org", "Cc": "zhangyin2018@iscas.ac.cn, zihongyao@outlook.com,\n Zihong Yao <zihong.plct@isrc.iscas.ac.cn>", "Subject": "[RFC PATCH 0/5] riscv: Add libmvec routines", "Date": "Mon, 9 Feb 2026 06:04:35 +0800", "Message-ID": "<20260208220454.51741-1-zihong.plct@isrc.iscas.ac.cn>", "X-Mailer": "git-send-email 2.47.3", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "qwCowAAHsGuICIlpA257Bw--.50153S2", "X-Coremail-Antispam": "1UD129KBjvJXoWxuFWDtFy8Xr43tF43tw1xuFg_yoW7WF47pa\n n5uryfCw15JrWxJrySv3WIqFWrJr1Fgrn8ur1Svw18JrWrAFWrArZ2v348XryIka48uryU\n u3Wq9F15Cw15AFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDU0xBIdaVrnRJUUUyq14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02\n 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j\n 6r4UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r1j6r\n 4UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xII\n jxv20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr\n 1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI48J\n MxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwV\n AFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6xIIjxv2\n 0xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20EY4\n v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AK\n xVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUozVbDUUUU", "X-Originating-IP": "[183.6.59.140]", "X-CM-SenderInfo": "p2lk00vjoszunw6l223fol2u1dvotugofq/", "X-BeenThere": "libc-alpha@sourceware.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Libc-alpha mailing list <libc-alpha.sourceware.org>", "List-Unsubscribe": "<https://sourceware.org/mailman/options/libc-alpha>,\n <mailto:libc-alpha-request@sourceware.org?subject=unsubscribe>", "List-Archive": "<https://sourceware.org/pipermail/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-request@sourceware.org?subject=help>", "List-Subscribe": "<https://sourceware.org/mailman/listinfo/libc-alpha>,\n <mailto:libc-alpha-request@sourceware.org?subject=subscribe>", "Errors-To": "libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org" }, "content": "From: Zihong Yao <zihong.plct@isrc.iscas.ac.cn>\n\nHi all,\n\nThis RFC adds initial RVV support for libmvec on RISC-V and uses vector\nlog/logf as the first users. The goal is to establish the basic structure\nfor build/export/abi-testing/benchmark works in RISC-V libmvec.\n\nBackground\n===========\nYulong Shi and Zhijin Zeng previously posted related RISC-V libmvec work[1].\nThis series takes a different integration approach and adds ABI checks and\nbenchtests.\n\nPerformance and accuracy\n=========================\nIn our local benchtests with SpacemiT X60, the RVV implementations show the\nfollowing speedups relative to the scalar libm functions:\n - logf: speedup up to 4x with LMUL=4 and SIMDLEN=32, and then collapses\n to 3x with LMUL=8 and SIMDLEN=64 due to register spilling. The\n register spilling appears with both GCC 15.2 and Clang 21 with -O3\n optimization and could be avoided by hand-written code.\n - log: speedup up to 2x with LMUL=2 and SIMDLEN=8, having the similar\n issues with logf with higher LMUL.\n\nAccuracy has been tested to be within <= 1 ULP compared with libm.\n\nFeedback requested\n===================\nFeedback on the points below is especially welcome, but any other review\ncomments are appreciated as well :)\n1. Layout/integration\n The current approach consists of:\n - common RVV helpers (e.g. v_math.h)\n - per-LMUL / per-SIMDLEN instantiations from a single implementation\n - list-driven symbol export, tests, and benchmark entry generation\n Is this structure acceptable for glibc, or is a different integration\n model preferred?\n\n2. Licensing\n The vector log routine is derived from veclibm [2].\n glibc seems to require a clear licensing. Beyond documenting sources in\n commit messages and source comments, are additional steps expected\n like FSF copyright assignment or an explicit relicensing statement\n from the original copyright holders?\n\n3. LMUL vs code generation\n With current GCC and Clang, logf exhibits noticeable register spilling\n for larger LMUL values (especially for LMUL > 4). This appears to be an\n optimization issue, and we find it could be avoided by handwriting assembly\n code versions.\n\n Would it be preferable to:\n a) provide hand-written assembly for some or all LMUL variants, or\n b) rely on future compiler improvements and keep the current pattern?\n\nThanks for any review,\nZihong\n\nReferences\n==========\n[1] https://inbox.sourceware.org/libc-alpha/20240415072108.3741341-1-shiyulong@iscas.ac.cn/\n[2] https://github.com/rivosinc/veclibm\n\n\nZihong Yao (5):\n riscv: libmvec: add RVV log and infrastructure\n riscv: libmvec: add ABI tests\n riscv: libmvec: add benchtests\n riscv: libmvec: add RVV logf\n riscv: libmvec: exercise RVV ABI calls\n\n sysdeps/aarch64/fpu/vecmath_config.h | 9 -\n sysdeps/generic/math_private.h | 9 +\n sysdeps/riscv/rvd/Makeconfig | 81 +++++\n sysdeps/riscv/rvd/Makefile | 93 ++++++\n sysdeps/riscv/rvd/Versions | 26 ++\n sysdeps/riscv/rvd/bench-libmvec-arch.h | 49 +++\n sysdeps/riscv/rvd/bits/math-vector.h | 25 ++\n .../riscv/rvd/scripts/bench_libmvec_rvv.py | 293 ++++++++++++++++++\n sysdeps/riscv/rvd/test-double-libmvec-log.c | 21 ++\n sysdeps/riscv/rvd/test-float-libmvec-logf.c | 21 ++\n sysdeps/riscv/rvd/test-vector-abi-arg1.h | 113 +++++++\n sysdeps/riscv/rvd/test-vector-abi.h | 36 +++\n sysdeps/riscv/rvd/v_d_log.c | 22 ++\n sysdeps/riscv/rvd/v_d_log_data.c | 152 +++++++++\n sysdeps/riscv/rvd/v_d_log_skeleton.c | 151 +++++++++\n sysdeps/riscv/rvd/v_f_logf.c | 22 ++\n sysdeps/riscv/rvd/v_f_logf_skeleton.c | 138 +++++++++\n sysdeps/riscv/rvd/v_math.h | 169 ++++++++++\n sysdeps/riscv/rvd/v_math_importer.h | 137 ++++++++\n sysdeps/riscv/rvd/v_math_names.h | 27 ++\n sysdeps/riscv/rvd/v_math_variants.h | 48 +++\n sysdeps/riscv/rvd/vecmath_config.h | 110 +++++++\n sysdeps/unix/sysv/linux/riscv/libmvec.abilist | 22 ++\n 23 files changed, 1765 insertions(+), 9 deletions(-)\n create mode 100644 sysdeps/riscv/rvd/Makeconfig\n create mode 100644 sysdeps/riscv/rvd/Makefile\n create mode 100644 sysdeps/riscv/rvd/Versions\n create mode 100644 sysdeps/riscv/rvd/bench-libmvec-arch.h\n create mode 100644 sysdeps/riscv/rvd/bits/math-vector.h\n create mode 100644 sysdeps/riscv/rvd/scripts/bench_libmvec_rvv.py\n create mode 100644 sysdeps/riscv/rvd/test-double-libmvec-log.c\n create mode 100644 sysdeps/riscv/rvd/test-float-libmvec-logf.c\n create mode 100644 sysdeps/riscv/rvd/test-vector-abi-arg1.h\n create mode 100644 sysdeps/riscv/rvd/test-vector-abi.h\n create mode 100644 sysdeps/riscv/rvd/v_d_log.c\n create mode 100644 sysdeps/riscv/rvd/v_d_log_data.c\n create mode 100644 sysdeps/riscv/rvd/v_d_log_skeleton.c\n create mode 100644 sysdeps/riscv/rvd/v_f_logf.c\n create mode 100644 sysdeps/riscv/rvd/v_f_logf_skeleton.c\n create mode 100644 sysdeps/riscv/rvd/v_math.h\n create mode 100644 sysdeps/riscv/rvd/v_math_importer.h\n create mode 100644 sysdeps/riscv/rvd/v_math_names.h\n create mode 100644 sysdeps/riscv/rvd/v_math_variants.h\n create mode 100644 sysdeps/riscv/rvd/vecmath_config.h\n create mode 100644 sysdeps/unix/sysv/linux/riscv/libmvec.abilist" }