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{ "id": 1191878, "url": "http://patchwork.ozlabs.org/api/covers/1191878/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/cover/20191108130123.6839-1-linux@rasmusvillemoes.dk/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20191108130123.6839-1-linux@rasmusvillemoes.dk/", "date": "2019-11-08T13:00:36", "name": "[v4,00/47] QUICC Engine support on ARM and ARM64", "submitter": { "id": 27394, "url": "http://patchwork.ozlabs.org/api/people/27394/?format=api", "name": "Rasmus Villemoes", "email": "linux@rasmusvillemoes.dk" }, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/cover/20191108130123.6839-1-linux@rasmusvillemoes.dk/mbox/", "series": [ { "id": 141654, "url": "http://patchwork.ozlabs.org/api/series/141654/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=141654", "date": "2019-11-08T13:00:38", "name": "QUICC Engine support on ARM and ARM64", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/141654/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/1191878/comments/", "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 478gw51vRLz9s4Y\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 00:24:05 +1100 (AEDT)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 478gw44rcyzF43s\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 00:24:03 +1100 (AEDT)", "from mail-lj1-x241.google.com (mail-lj1-x241.google.com\n\t[IPv6:2a00:1450:4864:20::241])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (2048 bits)\n\tserver-digest SHA256) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 478gQ75sP9zF6qJ\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 9 Nov 2019 00:01:32 +1100 (AEDT)", "by mail-lj1-x241.google.com with SMTP id e9so6088530ljp.13\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 08 Nov 2019 05:01:32 -0800 (PST)", "from prevas-ravi.prevas.se ([81.216.59.226])\n\tby smtp.gmail.com with ESMTPSA id\n\td28sm2454725lfn.33.2019.11.08.05.01.26\n\t(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n\tFri, 08 Nov 2019 05:01:27 -0800 (PST)" ], "Authentication-Results": [ "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"EuLkizYp\"; dkim-atps=neutral", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n\tsmtp.mailfrom=rasmusvillemoes.dk (client-ip=2a00:1450:4864:20::241;\n\thelo=mail-lj1-x241.google.com; envelope-from=linux@rasmusvillemoes.dk;\n\treceiver=<UNKNOWN>)", "lists.ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=rasmusvillemoes.dk", "lists.ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=rasmusvillemoes.dk header.i=@rasmusvillemoes.dk\n\theader.b=\"EuLkizYp\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=rasmusvillemoes.dk; s=google;\n\th=from:to:cc:subject:date:message-id:mime-version\n\t:content-transfer-encoding;\n\tbh=aUppc8s9ASNOkI1o9K2Lst5r5H5VsXnRIIZWwBaqYfY=;\n\tb=EuLkizYpSTSpkEM/mr4dp4416n7C84jLEe7ecnYWXenwWBfBjfuZjQkGtV2mKXjz9c\n\togoQ26VX01jwwPCVADFRvB7P1ASwck5FxA69ozpKQTHSsBRd3AuuWEtwHYSMgsojM4ft\n\tJ8aS+vpG8YrG+9l2s0YpXT78y34oXKvng8ggs=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version\n\t:content-transfer-encoding;\n\tbh=aUppc8s9ASNOkI1o9K2Lst5r5H5VsXnRIIZWwBaqYfY=;\n\tb=Gu0jfn29sMqEVKW+UnLhGREat9k7Nk2CINhEECG2WhfzI6PxvcJghI2Yt1zSuA3BCi\n\tkVOixK2/LdvcUo1XCuXC0ZzWHkqiWXNXyxZKui3crPDlhWnk6KB5Aap3g7gZdVATQQX3\n\tKHnDXhP5cmz1CkWQNMYIXFhTIvqQ+G8ndCg4+I4I7ZByt5raohRR47WrPmbreGj9YfRW\n\t/2OTZzqstYbIcHTANZpxGsPtqOC6PGv/TF3fQfy6r/IdWskd9R+8SeD2p7cS47ekhsHD\n\t7HpfM6v/VaPRrs0tmFYEg+ZS6vXL53fICdxfp8jOpEjR8dAhY2nsnqCsI0u9Kb3lWHSC\n\tYFUw==", "X-Gm-Message-State": "APjAAAXnbHORTA1+ulSqdkdxhs+lQK523Pu3qqyi6gzwebPEIZ+wLhyH\n\tU8lBGyevfwb8EGji4DuA/GL+kg==", "X-Google-Smtp-Source": "APXvYqw70GWgApN/AKmwBluJVMe7caQs3n1BnH98B/kLOROrcwFQYbVeqQkPiMWuAbM8jPxziHrQFg==", "X-Received": "by 2002:a2e:94d6:: with SMTP id r22mr6704965ljh.7.1573218087978; \n\tFri, 08 Nov 2019 05:01:27 -0800 (PST)", "From": "Rasmus Villemoes <linux@rasmusvillemoes.dk>", "To": "Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,\n\tChristophe Leroy <christophe.leroy@c-s.fr>", "Subject": "[PATCH v4 00/47] QUICC Engine support on ARM and ARM64", "Date": "Fri, 8 Nov 2019 14:00:36 +0100", "Message-Id": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "X-Mailer": "git-send-email 2.23.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Scott Wood <oss@buserror.net>,\n\tRasmus Villemoes <linux@rasmusvillemoes.dk>, \n\tlinuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "There have been several attempts in the past few years to allow\nbuilding the QUICC engine drivers for platforms other than PPC. This\nis yet another attempt.\n\nv3 can be found here: https://lore.kernel.org/lkml/20191101124210.14510-1-linux@rasmusvillemoes.dk/\n\nv4 adds a some patches to fix (ab)use of IS_ERR_VALUE which fails when\nsizeof(u32) != sizeof(long), i.e. on 64-bit platforms. Freescale\ndrivers are some of the last holdouts using that macro (outside of\narch/ and core mm code), so I decided trying to simply get rid of it\ninstead of papering over it by using a temporary long to store the\nresult in. Doing that I stumbled on some other things that should be\nfixed. These are the new patches 34-45.\n\nPatch 35 from v3 (which added a PPC32 dependency to FSL_UCC_HDLC) is\ngone from this version, so that that driver can indeed now be built\nfor arm and arm64.\n\n1-5 are about replacing in_be32 etc. in the core QE code (drivers/soc/fsl/qe).\n\n6-8 handle miscellaneous other ppcisms.\n\n9-21 deal with qe_ic: Simplifying the driver significantly by removing\nunused code, and removing the platform-specific initialization from\narch/powerpc/.\n\n22-25 deal with raw access to devicetree properties in native endianness.\n\n26-33 makes drivers/tty/serial/ucc_uart.c (CONFIG_SERIAL_QE) ready to build on arm.\n\n34-45 deal with IS_ERR_VALUE() and some other things found while\ndigging around that part of the code.\n\n46 adds a PPC32 dependency to UCC_GETH - it has some of the same\nissues that have been fixed in the ucc_uart and ucc_hdlc cases. Nobody\nhas requested that I allow that driver to be built for arm{,64}, so\ninstead of growing this series even bigger, I kept that addition. It's\ntrivial to remove if somebody cares enough to fix the build\nerrors/warnings and actually has a platform to test the result on.\n\nFinally patch 47 lifts the PPC32 restriction from QUICC_ENGINE. At the\nrequest of Li Yang, it doesn't remove the PPC32 dependency but instead\nchanges it to PPC32 || ARM || ARM64 (or COMPILE_TEST), i.e. listing\nthe platforms that may have a QE.\n\nThe series has been built and booted on both an mpc8309-based platform\n(ppc) as well as an ls1021a-based platform (arm). The core QE code is\nexercised on both, while I could only test the ucc_uart on arm, since\nthe uarts are not wired up on our mpc8309 board. Qiang Zhao reports\nthat the ucc_hdlc driver does indeed work on a ls1043ardb (arm64)\nboard, I hope he'll formally add a Tested-by: to the relevant patches\nsince I don't have any arm64 board with QE.\n\nRasmus Villemoes (47):\n soc: fsl: qe: remove space-before-tab\n soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs\n soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers\n soc: fsl: qe: introduce qe_io{read,write}* wrappers\n soc: fsl: qe: avoid ppc-specific io accessors\n soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic\n soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32\n soc: fsl: qe: drop unneeded #includes\n soc: fsl: qe: drop assign-only high_active in qe_ic_init\n soc: fsl: qe: remove pointless sysfs registration in qe_ic.c\n soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx\n soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/\n powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ\n powerpc/85xx: remove mostly pointless mpc85xx_qe_init()\n soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c\n soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low\n soc: fsl: qe: remove unused qe_ic_set_* functions\n soc: fsl: qe: don't use NO_IRQ in qe_ic.c\n soc: fsl: qe: make qe_ic_get_{low,high}_irq static\n soc: fsl: qe: simplify qe_ic_init()\n soc: fsl: qe: merge qe_ic.h headers into qe_ic.c\n soc: fsl: qe: qe.c: use of_property_read_* helpers\n soc: fsl: qe: qe_io.c: don't open-code of_parse_phandle()\n soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu\n soc: fsl: qe: qe_io.c: use of_property_read_u32() in par_io_init()\n soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl\n soc/fsl/qe/qe.h: update include path for cpm.h\n serial: ucc_uart: explicitly include soc/fsl/cpm.h\n serial: ucc_uart: replace ppc-specific IO accessors\n serial: ucc_uart: factor out soft_uart initialization\n serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32\n serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe()\n serial: ucc_uart: access __be32 field using be32_to_cpu\n soc: fsl: qe: change return type of cpm_muram_alloc() to s32\n soc: fsl: qe: make cpm_muram_free() return void\n soc: fsl: qe: make cpm_muram_free() ignore a negative offset\n soc: fsl: qe: drop broken lazy call of cpm_muram_init()\n soc: fsl: qe: refactor cpm_muram_alloc_common to prevent BUG on error\n path\n soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c\n soc: fsl: qe: drop use of IS_ERR_VALUE in qe_sdma_init()\n soc: fsl: qe: drop pointless check in qe_sdma_init()\n soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c\n net/wan/fsl_ucc_hdlc: avoid use of IS_ERR_VALUE()\n net/wan/fsl_ucc_hdlc: fix reading of __be16 registers\n net/wan/fsl_ucc_hdlc: reject muram offsets above 64K\n net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32\n soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE\n\n arch/powerpc/include/asm/cpm.h | 172 +-------\n arch/powerpc/platforms/83xx/km83xx.c | 3 +-\n arch/powerpc/platforms/83xx/misc.c | 23 --\n arch/powerpc/platforms/83xx/mpc832x_mds.c | 3 +-\n arch/powerpc/platforms/83xx/mpc832x_rdb.c | 3 +-\n arch/powerpc/platforms/83xx/mpc836x_mds.c | 3 +-\n arch/powerpc/platforms/83xx/mpc836x_rdk.c | 3 +-\n arch/powerpc/platforms/83xx/mpc83xx.h | 7 -\n arch/powerpc/platforms/85xx/common.c | 23 --\n arch/powerpc/platforms/85xx/corenet_generic.c | 12 -\n arch/powerpc/platforms/85xx/mpc85xx.h | 2 -\n arch/powerpc/platforms/85xx/mpc85xx_mds.c | 28 --\n arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 18 -\n arch/powerpc/platforms/85xx/twr_p102x.c | 16 -\n drivers/net/ethernet/freescale/Kconfig | 2 +-\n drivers/net/wan/fsl_ucc_hdlc.c | 23 +-\n drivers/net/wan/fsl_ucc_hdlc.h | 2 +-\n drivers/soc/fsl/qe/Kconfig | 3 +-\n drivers/soc/fsl/qe/gpio.c | 34 +-\n drivers/soc/fsl/qe/qe.c | 104 ++---\n drivers/soc/fsl/qe/qe_common.c | 50 +--\n drivers/soc/fsl/qe/qe_ic.c | 285 ++++++-------\n drivers/soc/fsl/qe/qe_ic.h | 99 -----\n drivers/soc/fsl/qe/qe_io.c | 70 ++--\n drivers/soc/fsl/qe/qe_tdm.c | 8 +-\n drivers/soc/fsl/qe/ucc.c | 26 +-\n drivers/soc/fsl/qe/ucc_fast.c | 86 ++--\n drivers/soc/fsl/qe/ucc_slow.c | 60 ++-\n drivers/soc/fsl/qe/usb.c | 2 +-\n drivers/tty/serial/ucc_uart.c | 383 +++++++++---------\n include/soc/fsl/cpm.h | 171 ++++++++\n include/soc/fsl/qe/qe.h | 59 ++-\n include/soc/fsl/qe/qe_ic.h | 135 ------\n include/soc/fsl/qe/ucc_fast.h | 4 +-\n include/soc/fsl/qe/ucc_slow.h | 6 +-\n 35 files changed, 770 insertions(+), 1158 deletions(-)\n delete mode 100644 drivers/soc/fsl/qe/qe_ic.h\n create mode 100644 include/soc/fsl/cpm.h\n delete mode 100644 include/soc/fsl/qe/qe_ic.h" }