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{ "id": 1117710, "url": "http://patchwork.ozlabs.org/api/covers/1117710/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/cover/1560843991-24123-1-git-send-email-skomatineni@nvidia.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "list_archive_url": null, "date": "2019-06-18T07:46:14", "name": "[V3,00/17] SC7 entry and exit support for Tegra210", "submitter": { "id": 75554, "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api", "name": "Sowjanya Komatineni", "email": "skomatineni@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/cover/1560843991-24123-1-git-send-email-skomatineni@nvidia.com/mbox/", "series": [ { "id": 114436, "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436", "date": "2019-06-18T07:46:16", "name": "SC7 entry and exit support for Tegra210", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/1117710/comments/", "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"c2n0y9rs\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgDp4h7yz9sBp\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:48:26 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1726023AbfFRHqi (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:46:38 -0400", "from hqemgate15.nvidia.com ([216.228.121.64]:19625 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1725870AbfFRHqi (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:46:38 -0400", "from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0896dc0000>; Tue, 18 Jun 2019 00:46:36 -0700", "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:46:35 -0700", "from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL106.nvidia.com\n\t(172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:35 +0000", "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:46:35 +0000", "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0896d90001>; Tue, 18 Jun 2019 00:46:35 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:46:35 -0700", "From": "Sowjanya Komatineni <skomatineni@nvidia.com>", "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>", "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>", "Subject": "[PATCH V3 00/17] SC7 entry and exit support for Tegra210", "Date": "Tue, 18 Jun 2019 00:46:14 -0700", "Message-ID": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "X-Mailer": "git-send-email 2.7.4", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560843996; bh=MwvRLxgw/Ex+WgwWlRPTWg792Ydrvex5zgIQoYyWuCY=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tX-NVConfidentiality:MIME-Version:Content-Type;\n\tb=c2n0y9rs3Lp6RAkxbHP0NVsS9Afbf0+QNHDjBb03WEfZzNWMX3bKkUcBDfVVpRgFp\n\tN2bSO+vMXIZb4dbTW9InLYUJ/TbzuWqfGzkd/+35dyzTqKBj+ZzirF5Xql52PBwsee\n\tSwRczKxMd/gPnI+yYP8ciwJ0EZNt1fcAdlPJ1e6MfrrxzH0IRN6Ow+JjCfUjZwYoSF\n\tgHOWe3WxdJjL+SkdZ7ozWLr7HZhYnq47X7+YmTaCkbhjsX7G14j2T4g6gUnL4uSxwa\n\tzjJuOeehwbpW4cfYUlM7DZRavE1oT5GGWN8ZGs+PvPKlBLYXmHqToryZUZMrDViuzZ\n\tXzmzOjltYAEDw==", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "This patch series includes Tegra210 deepsleep support with RTC alarm\nwake event.\n\nThis series also includes save and restore of PLLs, clocks, OSC contexts\nfor deepsleep exit to normal operation.\n\nThis patch series doesn't support 100% suspend/resume to allow fully\nfunctional state upon resume and we are working on some more drivers suspend\nand resume implementations.\n\n[V3]: Changes between V2 & V3 are\n\t- V2 feedback fixes\n\t- GPIO restore should happen prior to Pinctrl restore to prevent\n\t glitch on GPIO lines. So using resume_noirq for gpio tegra to allow\n\t gpio resume prior to pinctrl resume.\n\t- Implemented save_context and restore_context callbacks for clock\n\t plls, pll outs and dividers in corresponding drivers.\n\t Note: Peripheral clocks and clock enable and reset need to be in\n\t Tegra210 clock suspend/resume as they need to be in proper sequence\n\t w.r.t DFLL resume for restoring CPU clock.\n\t- Removed gpio-tegra changes for hierarchical support to have PMC as\n\t parent to GPIOs for GPIO wake event support. Thierry is working on\n\t gpiolib for some cleanup before adding hierarchical support. So\n\t holding on to GPIO wake support for now.\n\n[V2] : V1 feedback fixes\n\tPatch 0002: This version still using syscore. Thierry suggest not to\n\tuse syscore and waiting on suggestion from Linux Walleij for any better\n\tway of storing current state of pins before suspend entry and restoring\n\tthem on resume at very early stage. So left this the same way as V1 and\n\twill address once I get more feedback on this.\n\tAlso need to findout and implement proper way of forcing resume order\n\tbetween pinctrl and gpio driver.\n\n[V1]:\tTegra210 SC7 entry and exit thru RTC wake and Power button GPIO wake\n\tusing hierarchical IRQ with PMC as parent to GPIO.\n\n\nSowjanya Komatineni (17):\n irqchip: tegra: do not disable COP IRQ during suspend\n pinctrl: tegra: add suspend and resume support\n gpio: tegra: use resume_noirq for tegra gpio resume\n clk: tegra: save and restore divider rate\n clk: tegra: pllout: save and restore pllout context\n clk: tegra: pll: save and restore pll context\n clk: tegra: save and restore CPU and System clocks context\n clk: tegra: add support for peripheral clock suspend and resume\n clk: tegra: support for saving and restoring OSC clock context\n clk: tegra: add suspend resume support for DFLL\n clk: tegra210: support for Tegra210 clocks suspend and resume\n soc/tegra: pmc: allow support for more tegra wake\n soc/tegra: pmc: add pmc wake support for tegra210\n arm64: tegra: enable wake from deep sleep on RTC alarm.\n soc/tegra: pmc: configure core power request polarity\n soc/tegra: pmc: configure deep sleep control settings\n arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings\n\n arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 7 +\n arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +-\n drivers/clk/tegra/clk-dfll.c | 78 +++++++++\n drivers/clk/tegra/clk-dfll.h | 2 +\n drivers/clk/tegra/clk-divider.c | 23 +++\n drivers/clk/tegra/clk-pll-out.c | 28 ++++\n drivers/clk/tegra/clk-pll.c | 115 +++++++++----\n drivers/clk/tegra/clk-tegra-fixed.c | 14 ++\n drivers/clk/tegra/clk-tegra-super-gen4.c | 4 -\n drivers/clk/tegra/clk-tegra210.c | 218 ++++++++++++++++++++++++-\n drivers/clk/tegra/clk.c | 150 ++++++++++++++++-\n drivers/clk/tegra/clk.h | 29 +++-\n drivers/gpio/gpio-tegra.c | 17 +-\n drivers/irqchip/irq-tegra.c | 21 ++-\n drivers/pinctrl/tegra/pinctrl-tegra.c | 62 +++++++\n drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +\n drivers/pinctrl/tegra/pinctrl-tegra114.c | 1 +\n drivers/pinctrl/tegra/pinctrl-tegra124.c | 1 +\n drivers/pinctrl/tegra/pinctrl-tegra20.c | 1 +\n drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 ++\n drivers/pinctrl/tegra/pinctrl-tegra30.c | 1 +\n drivers/soc/tegra/pmc.c | 143 +++++++++++++++-\n 22 files changed, 880 insertions(+), 58 deletions(-)" }