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{
    "id": 500299,
    "url": "http://patchwork.ozlabs.org/api/1.2/series/500299/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500299",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
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        "scm_url": "",
        "webscm_url": "",
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    },
    "name": "Add RISC-V big-endian target support",
    "date": "2026-04-17T10:03:08",
    "submitter": {
        "id": 90738,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/90738/?format=api",
        "name": "Djordje Todorovic",
        "email": "Djordje.Todorovic@htecgroup.com"
    },
    "version": 7,
    "total": 6,
    "received_total": 6,
    "received_all": true,
    "mbox": "http://patchwork.ozlabs.org/series/500299/mbox/",
    "cover_letter": {
        "id": 2224342,
        "url": "http://patchwork.ozlabs.org/api/1.2/covers/2224342/?format=api",
        "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260417100302.162260-1-djordje.todorovic@htecgroup.com/",
        "msgid": "<20260417100302.162260-1-djordje.todorovic@htecgroup.com>",
        "list_archive_url": null,
        "date": "2026-04-17T10:03:08",
        "name": "[v7,0/6] Add RISC-V big-endian target support",
        "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260417100302.162260-1-djordje.todorovic@htecgroup.com/mbox/"
    },
    "patches": [
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            "date": "2026-04-17T10:03:09",
            "name": "[v7,1/6] target/riscv: Define MSTATUS_SBE and MSTATUS_MBE bit masks",
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        {
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            "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224344/?format=api",
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            "date": "2026-04-17T10:03:10",
            "name": "[v7,2/6] target/riscv: Add big-endian CPU property",
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        },
        {
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            "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224345/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417100302.162260-5-djordje.todorovic@htecgroup.com/",
            "msgid": "<20260417100302.162260-5-djordje.todorovic@htecgroup.com>",
            "list_archive_url": null,
            "date": "2026-04-17T10:03:11",
            "name": "[v7,4/6] hw/riscv: Make boot code endianness-aware at runtime",
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        },
        {
            "id": 2224348,
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            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260417100302.162260-4-djordje.todorovic@htecgroup.com/",
            "msgid": "<20260417100302.162260-4-djordje.todorovic@htecgroup.com>",
            "list_archive_url": null,
            "date": "2026-04-17T10:03:11",
            "name": "[v7,3/6] target/riscv: Implement runtime data endianness via MSTATUS bits",
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        },
        {
            "id": 2224347,
            "url": "http://patchwork.ozlabs.org/api/1.2/patches/2224347/?format=api",
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            "msgid": "<20260417100302.162260-6-djordje.todorovic@htecgroup.com>",
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            "date": "2026-04-17T10:03:12",
            "name": "[v7,5/6] target/riscv: Fix page table walk endianness for big-endian harts",
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        {
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            "msgid": "<20260417100302.162260-7-djordje.todorovic@htecgroup.com>",
            "list_archive_url": null,
            "date": "2026-04-17T10:03:14",
            "name": "[v7,6/6] target/riscv: Add test for RISC-V BE",
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}