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GET /api/1.2/patches/949201/?format=api
{ "id": 949201, "url": "http://patchwork.ozlabs.org/api/1.2/patches/949201/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20180725133152.30898-13-miquel.raynal@bootlin.com/", "project": { "id": 3, "url": "http://patchwork.ozlabs.org/api/1.2/projects/3/?format=api", "name": "Linux MTD development", "link_name": "linux-mtd", "list_id": "linux-mtd.lists.infradead.org", "list_email": "linux-mtd@lists.infradead.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20180725133152.30898-13-miquel.raynal@bootlin.com>", "list_archive_url": null, "date": "2018-07-25T13:31:47", "name": "[v5,12/17] mtd: rawnand: tegra: convert driver to nand_scan()", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "d902a3c5da250cb9f5c182675034ad997da3601d", "submitter": { "id": 73368, "url": "http://patchwork.ozlabs.org/api/1.2/people/73368/?format=api", "name": "Miquel Raynal", "email": "miquel.raynal@bootlin.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20180725133152.30898-13-miquel.raynal@bootlin.com/mbox/", "series": [ { "id": 57526, "url": "http://patchwork.ozlabs.org/api/1.2/series/57526/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=57526", "date": "2018-07-25T13:31:36", "name": "Allow dynamic allocations during NAND chip identification phase", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/57526/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/949201/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/949201/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org\n\t(client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=bootlin.com", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Nx4AankQ\"; \n\tdkim-atps=neutral" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2607:7c80:54:e::133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 41bGcg3MQlz9s29\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 25 Jul 2018 23:42:27 +1000 (AEST)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux))\n\tid 1fiK3U-00007j-CQ; Wed, 25 Jul 2018 13:42:16 +0000", "from mail.bootlin.com ([62.4.15.54])\n\tby bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux))\n\tid 1fiJu4-0000L0-Ti\n\tfor linux-mtd@lists.infradead.org; Wed, 25 Jul 2018 13:32:51 +0000", "by mail.bootlin.com (Postfix, from userid 110)\n\tid CF89020997; Wed, 25 Jul 2018 15:32:17 +0200 (CEST)", "from localhost.localdomain\n\t(AAubervilliers-681-1-78-122.w90-88.abo.wanadoo.fr [90.88.20.122])\n\tby mail.bootlin.com (Postfix) with ESMTPSA id A3DD120922;\n\tWed, 25 Jul 2018 15:31:59 +0200 (CEST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe:\n\tList-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References:\n\tIn-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID:\n\tContent-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc\n\t:Resent-Message-ID:List-Owner;\n\tbh=eFR+BHCwc/0Y102dg527D2mVK7tLuECuqe7z40b6jAE=;\n\tb=Nx4AankQTlih5gaXv/niWc1UNb\n\t2iNC/5+1HrHsswQNFzCX+zJHuQmtYizYiI2izgdHLvlMRDHwOYOrcsCCR7/sXxfoq1X2Ky9mLWq2V\n\tj33JGRutBqzcuTA5ROq140tHsNeJf4H6fEg2CiATHZf7rA3htN8RCL1Cgj4JWc/eOmD9YjuPrAhjw\n\tqb/kHZuxsFQnSMaO8v7CipY2UTsRrZp5fvxNFnCJbZYMMUQ5aLq4MxxBZLAMPBsJV9o5SIMZUZ0Lf\n\tMkdxwDF+gGZJXouLp32zW8mWAxw+FU94BYjyRAq+w0yHTcakfZezsvRcqGUrMULCwtfgdVJRr1/dw\n\tv7OuJbBA==;", "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0", "From": "Miquel Raynal <miquel.raynal@bootlin.com>", "To": "Boris Brezillon <boris.brezillon@bootlin.com>,\n\tRichard Weinberger <richard@nod.at>,\n\tDavid Woodhouse <dwmw2@infradead.org>, \n\tBrian Norris <computersforpeace@gmail.com>,\n\tMarek Vasut <marek.vasut@gmail.com>", "Subject": "[PATCH v5 12/17] mtd: rawnand: tegra: convert driver to nand_scan()", "Date": "Wed, 25 Jul 2018 15:31:47 +0200", "Message-Id": "<20180725133152.30898-13-miquel.raynal@bootlin.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20180725133152.30898-1-miquel.raynal@bootlin.com>", "References": "<20180725133152.30898-1-miquel.raynal@bootlin.com>", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20180725_063233_857718_D0C77A4C ", "X-CRM114-Status": "GOOD ( 17.58 )", "X-Spam-Score": "-0.0 (/)", "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-0.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [62.4.15.54 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record", "X-BeenThere": "linux-mtd@lists.infradead.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-mtd/>", "List-Post": "<mailto:linux-mtd@lists.infradead.org>", "List-Help": "<mailto:linux-mtd-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>", "Cc": "Lucas Stach <dev@lynxeye.de>, Wenyou Yang <wenyou.yang@microchip.com>,\n\tJosh Wu <rainyfeeling@outlook.com>, Stefan Agner <stefan@agner.ch>,\n\tlinux-mtd@lists.infradead.org, Miquel Raynal <miquel.raynal@bootlin.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>", "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "Two helpers have been added to the core to do all kind of controller\nside configuration/initialization between the detection phase and the\nfinal NAND scan. Implement these hooks so that we can convert the driver\nto just use nand_scan() instead of the nand_scan_ident() +\nnand_scan_tail() pair.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/mtd/nand/raw/tegra_nand.c | 162 +++++++++++++++++++++-----------------\n 1 file changed, 88 insertions(+), 74 deletions(-)", "diff": "diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c\nindex 31c0d9ca9d23..79da1efc88d1 100644\n--- a/drivers/mtd/nand/raw/tegra_nand.c\n+++ b/drivers/mtd/nand/raw/tegra_nand.c\n@@ -906,74 +906,13 @@ static int tegra_nand_select_strength(struct nand_chip *chip, int oobsize)\n \t\t\t\t bits_per_step, oobsize);\n }\n \n-static int tegra_nand_chips_init(struct device *dev,\n-\t\t\t\t struct tegra_nand_controller *ctrl)\n+static int tegra_nand_attach_chip(struct nand_chip *chip)\n {\n-\tstruct device_node *np = dev->of_node;\n-\tstruct device_node *np_nand;\n-\tint nsels, nchips = of_get_child_count(np);\n-\tstruct tegra_nand_chip *nand;\n-\tstruct mtd_info *mtd;\n-\tstruct nand_chip *chip;\n+\tstruct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);\n+\tstruct tegra_nand_chip *nand = to_tegra_chip(chip);\n+\tstruct mtd_info *mtd = nand_to_mtd(chip);\n \tint bits_per_step;\n \tint ret;\n-\tu32 cs;\n-\n-\tif (nchips != 1) {\n-\t\tdev_err(dev, \"Currently only one NAND chip supported\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\tnp_nand = of_get_next_child(np, NULL);\n-\n-\tnsels = of_property_count_elems_of_size(np_nand, \"reg\", sizeof(u32));\n-\tif (nsels != 1) {\n-\t\tdev_err(dev, \"Missing/invalid reg property\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\t/* Retrieve CS id, currently only single die NAND supported */\n-\tret = of_property_read_u32(np_nand, \"reg\", &cs);\n-\tif (ret) {\n-\t\tdev_err(dev, \"could not retrieve reg property: %d\\n\", ret);\n-\t\treturn ret;\n-\t}\n-\n-\tnand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);\n-\tif (!nand)\n-\t\treturn -ENOMEM;\n-\n-\tnand->cs[0] = cs;\n-\n-\tnand->wp_gpio = devm_gpiod_get_optional(dev, \"wp\", GPIOD_OUT_LOW);\n-\n-\tif (IS_ERR(nand->wp_gpio)) {\n-\t\tret = PTR_ERR(nand->wp_gpio);\n-\t\tdev_err(dev, \"Failed to request WP GPIO: %d\\n\", ret);\n-\t\treturn ret;\n-\t}\n-\n-\tchip = &nand->chip;\n-\tchip->controller = &ctrl->controller;\n-\n-\tmtd = nand_to_mtd(chip);\n-\n-\tmtd->dev.parent = dev;\n-\tmtd->owner = THIS_MODULE;\n-\n-\tnand_set_flash_node(chip, np_nand);\n-\n-\tif (!mtd->name)\n-\t\tmtd->name = \"tegra_nand\";\n-\n-\tchip->options = NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;\n-\tchip->exec_op = tegra_nand_exec_op;\n-\tchip->select_chip = tegra_nand_select_chip;\n-\tchip->setup_data_interface = tegra_nand_setup_data_interface;\n-\n-\tret = nand_scan_ident(mtd, 1, NULL);\n-\tif (ret)\n-\t\treturn ret;\n \n \tif (chip->bbt_options & NAND_BBT_USE_FLASH)\n \t\tchip->bbt_options |= NAND_BBT_NO_OOB;\n@@ -982,7 +921,8 @@ static int tegra_nand_chips_init(struct device *dev,\n \tchip->ecc.size = 512;\n \tchip->ecc.steps = mtd->writesize / chip->ecc.size;\n \tif (chip->ecc_step_ds != 512) {\n-\t\tdev_err(dev, \"Unsupported step size %d\\n\", chip->ecc_step_ds);\n+\t\tdev_err(ctrl->dev, \"Unsupported step size %d\\n\",\n+\t\t\tchip->ecc_step_ds);\n \t\treturn -EINVAL;\n \t}\n \n@@ -1004,14 +944,15 @@ static int tegra_nand_chips_init(struct device *dev,\n \t}\n \n \tif (chip->ecc.algo == NAND_ECC_BCH && mtd->writesize < 2048) {\n-\t\tdev_err(dev, \"BCH supports 2K or 4K page size only\\n\");\n+\t\tdev_err(ctrl->dev, \"BCH supports 2K or 4K page size only\\n\");\n \t\treturn -EINVAL;\n \t}\n \n \tif (!chip->ecc.strength) {\n \t\tret = tegra_nand_select_strength(chip, mtd->oobsize);\n \t\tif (ret < 0) {\n-\t\t\tdev_err(dev, \"No valid strength found, minimum %d\\n\",\n+\t\t\tdev_err(ctrl->dev,\n+\t\t\t\t\"No valid strength found, minimum %d\\n\",\n \t\t\t\tchip->ecc_strength_ds);\n \t\t\treturn ret;\n \t\t}\n@@ -1039,7 +980,7 @@ static int tegra_nand_chips_init(struct device *dev,\n \t\t\tnand->config_ecc |= CONFIG_TVAL_8;\n \t\t\tbreak;\n \t\tdefault:\n-\t\t\tdev_err(dev, \"ECC strength %d not supported\\n\",\n+\t\t\tdev_err(ctrl->dev, \"ECC strength %d not supported\\n\",\n \t\t\t\tchip->ecc.strength);\n \t\t\treturn -EINVAL;\n \t\t}\n@@ -1062,17 +1003,17 @@ static int tegra_nand_chips_init(struct device *dev,\n \t\t\tnand->bch_config |= BCH_TVAL_16;\n \t\t\tbreak;\n \t\tdefault:\n-\t\t\tdev_err(dev, \"ECC strength %d not supported\\n\",\n+\t\t\tdev_err(ctrl->dev, \"ECC strength %d not supported\\n\",\n \t\t\t\tchip->ecc.strength);\n \t\t\treturn -EINVAL;\n \t\t}\n \t\tbreak;\n \tdefault:\n-\t\tdev_err(dev, \"ECC algorithm not supported\\n\");\n+\t\tdev_err(ctrl->dev, \"ECC algorithm not supported\\n\");\n \t\treturn -EINVAL;\n \t}\n \n-\tdev_info(dev, \"Using %s with strength %d per 512 byte step\\n\",\n+\tdev_info(ctrl->dev, \"Using %s with strength %d per 512 byte step\\n\",\n \t\t chip->ecc.algo == NAND_ECC_BCH ? \"BCH\" : \"RS\",\n \t\t chip->ecc.strength);\n \n@@ -1095,7 +1036,8 @@ static int tegra_nand_chips_init(struct device *dev,\n \t\tnand->config |= CONFIG_PS_4096;\n \t\tbreak;\n \tdefault:\n-\t\tdev_err(dev, \"Unsupported writesize %d\\n\", mtd->writesize);\n+\t\tdev_err(ctrl->dev, \"Unsupported writesize %d\\n\",\n+\t\t\tmtd->writesize);\n \t\treturn -ENODEV;\n \t}\n \n@@ -1106,7 +1048,78 @@ static int tegra_nand_chips_init(struct device *dev,\n \tnand->config |= CONFIG_TAG_BYTE_SIZE(mtd->oobsize - 1);\n \twritel_relaxed(nand->config, ctrl->regs + CONFIG);\n \n-\tret = nand_scan_tail(mtd);\n+\treturn 0;\n+}\n+\n+static const struct nand_controller_ops tegra_nand_controller_ops = {\n+\t.attach_chip = &tegra_nand_attach_chip,\n+};\n+\n+static int tegra_nand_chips_init(struct device *dev,\n+\t\t\t\t struct tegra_nand_controller *ctrl)\n+{\n+\tstruct device_node *np = dev->of_node;\n+\tstruct device_node *np_nand;\n+\tint nsels, nchips = of_get_child_count(np);\n+\tstruct tegra_nand_chip *nand;\n+\tstruct mtd_info *mtd;\n+\tstruct nand_chip *chip;\n+\tint ret;\n+\tu32 cs;\n+\n+\tif (nchips != 1) {\n+\t\tdev_err(dev, \"Currently only one NAND chip supported\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tnp_nand = of_get_next_child(np, NULL);\n+\n+\tnsels = of_property_count_elems_of_size(np_nand, \"reg\", sizeof(u32));\n+\tif (nsels != 1) {\n+\t\tdev_err(dev, \"Missing/invalid reg property\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Retrieve CS id, currently only single die NAND supported */\n+\tret = of_property_read_u32(np_nand, \"reg\", &cs);\n+\tif (ret) {\n+\t\tdev_err(dev, \"could not retrieve reg property: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tnand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);\n+\tif (!nand)\n+\t\treturn -ENOMEM;\n+\n+\tnand->cs[0] = cs;\n+\n+\tnand->wp_gpio = devm_gpiod_get_optional(dev, \"wp\", GPIOD_OUT_LOW);\n+\n+\tif (IS_ERR(nand->wp_gpio)) {\n+\t\tret = PTR_ERR(nand->wp_gpio);\n+\t\tdev_err(dev, \"Failed to request WP GPIO: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tchip = &nand->chip;\n+\tchip->controller = &ctrl->controller;\n+\n+\tmtd = nand_to_mtd(chip);\n+\n+\tmtd->dev.parent = dev;\n+\tmtd->owner = THIS_MODULE;\n+\n+\tnand_set_flash_node(chip, np_nand);\n+\n+\tif (!mtd->name)\n+\t\tmtd->name = \"tegra_nand\";\n+\n+\tchip->options = NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;\n+\tchip->exec_op = tegra_nand_exec_op;\n+\tchip->select_chip = tegra_nand_select_chip;\n+\tchip->setup_data_interface = tegra_nand_setup_data_interface;\n+\n+\tret = nand_scan(mtd, 1);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1137,6 +1150,7 @@ static int tegra_nand_probe(struct platform_device *pdev)\n \n \tctrl->dev = &pdev->dev;\n \tnand_controller_init(&ctrl->controller);\n+\tctrl->controller.ops = &tegra_nand_controller_ops;\n \n \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n \tctrl->regs = devm_ioremap_resource(&pdev->dev, res);\n", "prefixes": [ "v5", "12/17" ] }