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GET /api/1.2/patches/834176/?format=api
{ "id": 834176, "url": "http://patchwork.ozlabs.org/api/1.2/patches/834176/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/20171104085030.25430-4-saeedm@mellanox.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/1.2/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20171104085030.25430-4-saeedm@mellanox.com>", "list_archive_url": null, "date": "2017-11-04T08:50:21", "name": "[net-next,03/12] net/mlx5: Add MLX5_SET16 and MLX5_GET16", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "89cb726cc97bd18dcbb7cb205d0d7bec3005ef26", "submitter": { "id": 65299, "url": "http://patchwork.ozlabs.org/api/1.2/people/65299/?format=api", "name": "Saeed Mahameed", "email": "saeedm@mellanox.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/1.2/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/20171104085030.25430-4-saeedm@mellanox.com/mbox/", "series": [ { "id": 11869, "url": "http://patchwork.ozlabs.org/api/1.2/series/11869/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=11869", "date": "2017-11-04T08:50:18", "name": "[net-next,01/12] net/dcb: Add dscp to priority selector type", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/11869/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/834176/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/834176/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yTXdN1BWsz9sBW\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 4 Nov 2017 19:52:24 +1100 (AEDT)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932152AbdKDIwL (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tSat, 4 Nov 2017 04:52:11 -0400", "from mail-il-dmz.mellanox.com ([193.47.165.129]:54466 \"EHLO\n\tmellanox.co.il\" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org\n\twith ESMTP id S1755964AbdKDIwA (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Sat, 4 Nov 2017 04:52:00 -0400", "from Internal Mail-Server by MTLPINE1 (envelope-from\n\tsaeedm@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 4 Nov 2017 10:51:53 +0200", "from mti-swat15.mti.labs.mlnx. (mti-swat15.mti.labs.mlnx\n\t[10.20.1.123])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id vA48pkiR022678;\n\tSat, 4 Nov 2017 10:51:52 +0200" ], "From": "Saeed Mahameed <saeedm@mellanox.com>", "To": "\"David S. Miller\" <davem@davemloft.net>", "Cc": "netdev@vger.kernel.org, Huy Nguyen <huyn@mellanox.com>,\n\tSaeed Mahameed <saeedm@mellanox.com>", "Subject": "[net-next 03/12] net/mlx5: Add MLX5_SET16 and MLX5_GET16", "Date": "Sat, 4 Nov 2017 01:50:21 -0700", "Message-Id": "<20171104085030.25430-4-saeedm@mellanox.com>", "X-Mailer": "git-send-email 2.14.2", "In-Reply-To": "<20171104085030.25430-1-saeedm@mellanox.com>", "References": "<20171104085030.25430-1-saeedm@mellanox.com>", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "From: Huy Nguyen <huyn@mellanox.com>\n\nAdd MLX5_SET16 and MLX5_GET16 for 16bit structure field in firmware\ncommand.\n\nSigned-off-by: Huy Nguyen <huyn@mellanox.com>\nReviewed-by: Parav Pandit <parav@mellanox.com>\nSigned-off-by: Saeed Mahameed <saeedm@mellanox.com>\n---\n include/linux/mlx5/device.h | 17 +++++++++++++++++\n 1 file changed, 17 insertions(+)", "diff": "diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h\nindex 6d79b3f79458..409ffb14298a 100644\n--- a/include/linux/mlx5/device.h\n+++ b/include/linux/mlx5/device.h\n@@ -49,11 +49,15 @@\n #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)\n #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)\n #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))\n+#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)\n #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)\n #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)\n+#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))\n #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))\n #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))\n #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))\n+#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))\n+#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))\n #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)\n \n #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)\n@@ -116,6 +120,19 @@ __mlx5_mask(typ, fld))\n \t___t; \\\n })\n \n+#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\\\n+__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \\\n+__mlx5_mask16(typ, fld))\n+\n+#define MLX5_SET16(typ, p, fld, v) do { \\\n+\tu16 _v = v; \\\n+\tBUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \\\n+\t*((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \\\n+\tcpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \\\n+\t\t (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \\\n+\t\t << __mlx5_16_bit_off(typ, fld))); \\\n+} while (0)\n+\n /* Big endian getters */\n #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\\\n \t__mlx5_64_off(typ, fld)))\n", "prefixes": [ "net-next", "03/12" ] }