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GET /api/1.2/patches/833359/?format=api
{ "id": 833359, "url": "http://patchwork.ozlabs.org/api/1.2/patches/833359/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20171102135656.GE91830@kam.mff.cuni.cz/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.2/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20171102135656.GE91830@kam.mff.cuni.cz>", "list_archive_url": null, "date": "2017-11-02T13:56:57", "name": "Enable inc/dec generation on Haswell+", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "75b54687ec793afb150754be98f9168d2aa88acd", "submitter": { "id": 4327, "url": "http://patchwork.ozlabs.org/api/1.2/people/4327/?format=api", "name": "Jan Hubicka", "email": "hubicka@ucw.cz" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20171102135656.GE91830@kam.mff.cuni.cz/mbox/", "series": [ { "id": 11507, "url": "http://patchwork.ozlabs.org/api/1.2/series/11507/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=11507", "date": "2017-11-02T13:56:57", "name": "Enable inc/dec generation on Haswell+", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/11507/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/833359/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/833359/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-return-465749-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-465749-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"dUCuWIQT\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3ySRV74tvxz9t2M\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 3 Nov 2017 00:57:19 +1100 (AEDT)", "(qmail 77832 invoked by alias); 2 Nov 2017 13:57:02 -0000", "(qmail 76553 invoked by uid 89); 2 Nov 2017 13:57:01 -0000", "from nikam.ms.mff.cuni.cz (HELO nikam.ms.mff.cuni.cz)\n\t(195.113.20.16) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tThu, 02 Nov 2017 13:56:59 +0000", "by nikam.ms.mff.cuni.cz (Postfix, from userid 16202)\tid\n\t1A1925491A1; Thu, 2 Nov 2017 14:56:57 +0100 (CET)" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:date\n\t:from:to:subject:message-id:mime-version:content-type; q=dns; s=\n\tdefault; b=vU2UJVc89vj7TeEWkwAwIzqS2VQ3D4WdQ7mgrMgdGg6ZAcOK1loXt\n\tVHkjOAfuuFT7G7Fj9fEN4yNjZhS/s9mg6+K4VVDaop2P8lsZ+Z5+PnRvCamUxGGq\n\tGN57gcwCdUviDVgg6+3ma52iZhZJlViENm8xDh1+ti2ljIgZufEvmg=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender:date\n\t:from:to:subject:message-id:mime-version:content-type; s=\n\tdefault; bh=QCYjQSUWX99S+IG+DJz3fTOCi6I=; b=dUCuWIQTeiz35lQiUos+\n\tcrC4igTJg4suGkLHbYkab3+HIykMP5rOYSXZf3elnxxgTOT7XKa9Yyv/VVVv5WjI\n\th9gjGkqQOf9c8sYjWKzNwTQ802tE+GpaYgoG6JImi08cscrFYC6l1QoeX7YL9UUy\n\tG7RiLphtnVlPyH/+DnwRoRc=", "Mailing-List": "contact gcc-patches-help@gcc.gnu.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>", "List-Archive": "<http://gcc.gnu.org/ml/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-help@gcc.gnu.org>", "Sender": "gcc-patches-owner@gcc.gnu.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-10.3 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_2, GIT_PATCH_3, KAM_LAZY_DOMAIN_SECURITY,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Ivy, Sandy,\n\tsandy, measurable", "X-HELO": "nikam.ms.mff.cuni.cz", "Date": "Thu, 2 Nov 2017 14:56:57 +0100", "From": "Jan Hubicka <hubicka@ucw.cz>", "To": "gcc-patches@gcc.gnu.org", "Subject": "Enable inc/dec generation on Haswell+", "Message-ID": "<20171102135656.GE91830@kam.mff.cuni.cz>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "User-Agent": "Mutt/1.5.23 (2014-03-12)" }, "content": "Hi,\ncore2 used to have quite large penalty for partial flag registers store\ndone by INCDEC. This was improved on Sandybridge where extra merging uop\nis produced and more at Haswell where there is no extra uop unless there\nis instruction accessing both. For this reason we can use inc/dec again\non modern variants of core.\n\nBootstrapped/regtested x86_64-linux and tested on Haswell spec2k/spec2k6\nwith no measurable performance impact.\n\nHonza\n\n\t* x86-tune.def (X86_TUNE_USE_INCDEC): Enable for Haswell+.", "diff": "Index: config/i386/x86-tune.def\n===================================================================\n--- config/i386/x86-tune.def\t(revision 254199)\n+++ config/i386/x86-tune.def\t(working copy)\n@@ -220,10 +220,15 @@ DEF_TUNE (X86_TUNE_LCP_STALL, \"lcp_stall\n as \"add mem, reg\". */\n DEF_TUNE (X86_TUNE_READ_MODIFY, \"read_modify\", ~(m_PENT | m_LAKEMONT | m_PPRO))\n \n-/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions. */\n+/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.\n+\n+ Core2 and nehalem has stall of 7 cycles for partial flag register stalls.\n+ Sandy bridge and Ivy bridge generate extra uop. On Haswell this extra uop\n+ is output only when the values needs to be really merged, which is not\n+ done by GCC generated code. */\n DEF_TUNE (X86_TUNE_USE_INCDEC, \"use_incdec\",\n- ~(m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL\n-\t | m_KNL | m_KNM | m_GENERIC))\n+ ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE\n+\t | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GENERIC))\n \n /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred\n for DFmode copies */\n", "prefixes": [] }