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GET /api/1.2/patches/833322/?format=api
{ "id": 833322, "url": "http://patchwork.ozlabs.org/api/1.2/patches/833322/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/1509626723-18619-6-git-send-email-lipeng321@huawei.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/1.2/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1509626723-18619-6-git-send-email-lipeng321@huawei.com>", "list_archive_url": null, "date": "2017-11-02T12:45:19", "name": "[V2,net-next,5/9] net: hns3: Add reset process in hclge_main", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "16dd618a538df269342e8d1f3f6b2e7f79be8e36", "submitter": { "id": 71468, "url": "http://patchwork.ozlabs.org/api/1.2/people/71468/?format=api", "name": "lipeng (Y)", "email": "lipeng321@huawei.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/1.2/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/1509626723-18619-6-git-send-email-lipeng321@huawei.com/mbox/", "series": [ { "id": 11493, "url": "http://patchwork.ozlabs.org/api/1.2/series/11493/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=11493", "date": "2017-11-02T12:45:16", "name": "net: hns3: add support for reset", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/11493/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/833322/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/833322/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3ySPLP4Q5hz9t30\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 2 Nov 2017 23:20:29 +1100 (AEDT)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754987AbdKBMUP (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tThu, 2 Nov 2017 08:20:15 -0400", "from szxga06-in.huawei.com ([45.249.212.32]:51498 \"EHLO huawei.com\"\n\trhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1754855AbdKBMTH (ORCPT <rfc822;netdev@vger.kernel.org>);\n\tThu, 2 Nov 2017 08:19:07 -0400", "from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.59])\n\tby Forcepoint Email with ESMTP id CC81481829877;\n\tThu, 2 Nov 2017 20:18:50 +0800 (CST)", "from linux-ioko.site (10.71.200.31) by\n\tDGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP\n\tServer id 14.3.361.1; Thu, 2 Nov 2017 20:17:48 +0800" ], "From": "Lipeng <lipeng321@huawei.com>", "To": "<davem@davemloft.net>", "CC": "<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<linuxarm@huawei.com>, <salil.mehta@huawei.com>, <lipeng321@huawei.com>", "Subject": "[PATCH V2 net-next 5/9] net: hns3: Add reset process in hclge_main", "Date": "Thu, 2 Nov 2017 20:45:19 +0800", "Message-ID": "<1509626723-18619-6-git-send-email-lipeng321@huawei.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1509626723-18619-1-git-send-email-lipeng321@huawei.com>", "References": "<1509626723-18619-1-git-send-email-lipeng321@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.71.200.31]", "X-CFilter-Loop": "Reflected", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "This patch adds reset support for PF,it include : global reset, core reset,\nIMP reset, PF reset.The core reset will Reset all datapath of all functions\nexcept IMP, MAC and PCI interface. Global reset is equal with the core\nreset plus all MAC reset. IMP reset is caused by watchdog timer expiration,\nthe same with core reset in the reset flow. PF reset will reset whole\nphysical function.\n\nSigned-off-by: qumingguang <qumingguang@huawei.com>\nSigned-off-by: Lipeng <lipeng321@huawei.com>\nSigned-off-by: Yunsheng Lin <linyunsheng@huawei.com>\n---\n drivers/net/ethernet/hisilicon/hns3/hnae3.h | 19 ++\n .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 7 +\n .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 285 +++++++++++++++++++++\n .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 15 ++\n 4 files changed, 326 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h\nindex 3acd8db..67c59e1 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h\n@@ -110,6 +110,21 @@ enum hnae3_media_type {\n \tHNAE3_MEDIA_TYPE_BACKPLANE,\n };\n \n+enum hnae3_reset_notify_type {\n+\tHNAE3_UP_CLIENT,\n+\tHNAE3_DOWN_CLIENT,\n+\tHNAE3_INIT_CLIENT,\n+\tHNAE3_UNINIT_CLIENT,\n+};\n+\n+enum hnae3_reset_type {\n+\tHNAE3_FUNC_RESET,\n+\tHNAE3_CORE_RESET,\n+\tHNAE3_GLOBAL_RESET,\n+\tHNAE3_IMP_RESET,\n+\tHNAE3_NONE_RESET,\n+};\n+\n struct hnae3_vector_info {\n \tu8 __iomem *io_addr;\n \tint vector;\n@@ -133,6 +148,8 @@ struct hnae3_client_ops {\n \tvoid (*uninit_instance)(struct hnae3_handle *handle, bool reset);\n \tvoid (*link_status_change)(struct hnae3_handle *handle, bool state);\n \tint (*setup_tc)(struct hnae3_handle *handle, u8 tc);\n+\tint (*reset_notify)(struct hnae3_handle *handle,\n+\t\t\t enum hnae3_reset_notify_type type);\n };\n \n #define HNAE3_CLIENT_NAME_LENGTH 16\n@@ -367,6 +384,8 @@ struct hnae3_ae_ops {\n \t\t\t u16 vlan_id, bool is_kill);\n \tint (*set_vf_vlan_filter)(struct hnae3_handle *handle, int vfid,\n \t\t\t\t u16 vlan, u8 qos, __be16 proto);\n+\tvoid (*reset_event)(struct hnae3_handle *handle,\n+\t\t\t enum hnae3_reset_type reset);\n };\n \n struct hnae3_dcb_ops {\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\nindex db4d887..844c83e 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\n@@ -697,6 +697,13 @@ struct hclge_reset_tqp_queue_cmd {\n \tu8 rsv[20];\n };\n \n+#define HCLGE_CFG_RESET_MAC_B\t\t3\n+#define HCLGE_CFG_RESET_FUNC_B\t\t7\n+struct hclge_reset_cmd {\n+\tu8 mac_func_reset;\n+\tu8 fun_reset_vfid;\n+\tu8 rsv[22];\n+};\n #define HCLGE_DEFAULT_TX_BUF\t\t0x4000\t /* 16k bytes */\n #define HCLGE_TOTAL_PKT_BUF\t\t0x108000 /* 1.03125M bytes */\n #define HCLGE_DEFAULT_DV\t\t0xA000\t /* 40k byte */\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\nindex e45842e..699983a 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\n@@ -35,6 +35,7 @@ static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,\n \t\t\t\t enum hclge_mta_dmac_sel_type mta_mac_sel,\n \t\t\t\t bool enable);\n static int hclge_init_vlan_config(struct hclge_dev *hdev);\n+static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);\n \n static struct hnae3_ae_algo ae_algo;\n \n@@ -2446,8 +2447,212 @@ static int hclge_misc_irq_init(struct hclge_dev *hdev)\n \treturn ret;\n }\n \n+static int hclge_notify_client(struct hclge_dev *hdev,\n+\t\t\t enum hnae3_reset_notify_type type)\n+{\n+\tstruct hnae3_client *client = hdev->nic_client;\n+\tu16 i;\n+\n+\tif (!client->ops->reset_notify)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tfor (i = 0; i < hdev->num_vmdq_vport + 1; i++) {\n+\t\tstruct hnae3_handle *handle = &hdev->vport[i].nic;\n+\t\tint ret;\n+\n+\t\tret = client->ops->reset_notify(handle, type);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int hclge_reset_wait(struct hclge_dev *hdev)\n+{\n+#define HCLGE_RESET_WATI_MS\t100\n+#define HCLGE_RESET_WAIT_CNT\t5\n+\tu32 val, reg, reg_bit;\n+\tu32 cnt = 0;\n+\n+\tswitch (hdev->reset_type) {\n+\tcase HNAE3_GLOBAL_RESET:\n+\t\treg = HCLGE_GLOBAL_RESET_REG;\n+\t\treg_bit = HCLGE_GLOBAL_RESET_BIT;\n+\t\tbreak;\n+\tcase HNAE3_CORE_RESET:\n+\t\treg = HCLGE_GLOBAL_RESET_REG;\n+\t\treg_bit = HCLGE_CORE_RESET_BIT;\n+\t\tbreak;\n+\tcase HNAE3_FUNC_RESET:\n+\t\treg = HCLGE_FUN_RST_ING;\n+\t\treg_bit = HCLGE_FUN_RST_ING_B;\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(&hdev->pdev->dev,\n+\t\t\t\"Wait for unsupported reset type: %d\\n\",\n+\t\t\thdev->reset_type);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tval = hclge_read_dev(&hdev->hw, reg);\n+\twhile (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {\n+\t\tmsleep(HCLGE_RESET_WATI_MS);\n+\t\tval = hclge_read_dev(&hdev->hw, reg);\n+\t\tcnt++;\n+\t}\n+\n+\t/* must clear reset status register to\n+\t * prevent driver detect reset interrupt again\n+\t */\n+\treg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);\n+\thclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, reg);\n+\n+\tif (cnt >= HCLGE_RESET_WAIT_CNT) {\n+\t\tdev_warn(&hdev->pdev->dev,\n+\t\t\t \"Wait for reset timeout: %d\\n\", hdev->reset_type);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)\n+{\n+\tstruct hclge_desc desc;\n+\tstruct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;\n+\tint ret;\n+\n+\thclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);\n+\thnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);\n+\thnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);\n+\treq->fun_reset_vfid = func_id;\n+\n+\tret = hclge_cmd_send(&hdev->hw, &desc, 1);\n+\tif (ret)\n+\t\tdev_err(&hdev->pdev->dev,\n+\t\t\t\"send function reset cmd fail, status =%d\\n\", ret);\n+\n+\treturn ret;\n+}\n+\n+static void hclge_do_reset(struct hclge_dev *hdev, enum hnae3_reset_type type)\n+{\n+\tstruct pci_dev *pdev = hdev->pdev;\n+\tu32 val;\n+\n+\tswitch (type) {\n+\tcase HNAE3_GLOBAL_RESET:\n+\t\tval = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);\n+\t\thnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);\n+\t\thclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);\n+\t\tdev_info(&pdev->dev, \"Global Reset requested\\n\");\n+\t\tbreak;\n+\tcase HNAE3_CORE_RESET:\n+\t\tval = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);\n+\t\thnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);\n+\t\thclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);\n+\t\tdev_info(&pdev->dev, \"Core Reset requested\\n\");\n+\t\tbreak;\n+\tcase HNAE3_FUNC_RESET:\n+\t\tdev_info(&pdev->dev, \"PF Reset requested\\n\");\n+\t\thclge_func_reset_cmd(hdev, 0);\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_warn(&pdev->dev,\n+\t\t\t \"Unsupported reset type: %d\\n\", type);\n+\t\tbreak;\n+\t}\n+}\n+\n+static enum hnae3_reset_type hclge_detected_reset_event(struct hclge_dev *hdev)\n+{\n+\tenum hnae3_reset_type rst_level = HNAE3_NONE_RESET;\n+\tu32 rst_reg_val;\n+\n+\trst_reg_val = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);\n+\tif (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_reg_val)\n+\t\trst_level = HNAE3_GLOBAL_RESET;\n+\telse if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_reg_val)\n+\t\trst_level = HNAE3_CORE_RESET;\n+\telse if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_reg_val)\n+\t\trst_level = HNAE3_IMP_RESET;\n+\n+\treturn rst_level;\n+}\n+\n+static void hclge_reset_event(struct hnae3_handle *handle,\n+\t\t\t enum hnae3_reset_type reset)\n+{\n+\tstruct hclge_vport *vport = hclge_get_vport(handle);\n+\tstruct hclge_dev *hdev = vport->back;\n+\n+\tdev_info(&hdev->pdev->dev,\n+\t\t \"Receive reset event , reset_type is %d\", reset);\n+\n+\tswitch (reset) {\n+\tcase HNAE3_FUNC_RESET:\n+\tcase HNAE3_CORE_RESET:\n+\tcase HNAE3_GLOBAL_RESET:\n+\t\tif (test_bit(HCLGE_STATE_RESET_INT, &hdev->state)) {\n+\t\t\tdev_err(&hdev->pdev->dev, \"Already in reset state\");\n+\t\t\treturn;\n+\t\t}\n+\t\thdev->reset_type = reset;\n+\t\tset_bit(HCLGE_STATE_RESET_INT, &hdev->state);\n+\t\tset_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);\n+\t\tschedule_work(&hdev->service_task);\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_warn(&hdev->pdev->dev, \"Unsupported reset event:%d\", reset);\n+\t\tbreak;\n+\t}\n+}\n+\n+static void hclge_reset_subtask(struct hclge_dev *hdev)\n+{\n+\tbool do_reset;\n+\n+\tdo_reset = hdev->reset_type != HNAE3_NONE_RESET;\n+\n+\t/* Reset is detected by interrupt */\n+\tif (hdev->reset_type == HNAE3_NONE_RESET)\n+\t\thdev->reset_type = hclge_detected_reset_event(hdev);\n+\n+\tif (hdev->reset_type == HNAE3_NONE_RESET)\n+\t\treturn;\n+\n+\tswitch (hdev->reset_type) {\n+\tcase HNAE3_FUNC_RESET:\n+\tcase HNAE3_CORE_RESET:\n+\tcase HNAE3_GLOBAL_RESET:\n+\tcase HNAE3_IMP_RESET:\n+\t\thclge_notify_client(hdev, HNAE3_DOWN_CLIENT);\n+\n+\t\tif (do_reset)\n+\t\t\thclge_do_reset(hdev, hdev->reset_type);\n+\t\telse\n+\t\t\tset_bit(HCLGE_STATE_RESET_INT, &hdev->state);\n+\n+\t\tif (!hclge_reset_wait(hdev)) {\n+\t\t\thclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);\n+\t\t\thclge_reset_ae_dev(hdev->ae_dev);\n+\t\t\thclge_notify_client(hdev, HNAE3_INIT_CLIENT);\n+\t\t\tclear_bit(HCLGE_STATE_RESET_INT, &hdev->state);\n+\t\t}\n+\t\thclge_notify_client(hdev, HNAE3_UP_CLIENT);\n+\t\tbreak;\n+\tdefault:\n+\t\tdev_err(&hdev->pdev->dev, \"Unsupported reset type:%d\\n\",\n+\t\t\thdev->reset_type);\n+\t\tbreak;\n+\t}\n+\thdev->reset_type = HNAE3_NONE_RESET;\n+}\n+\n static void hclge_misc_irq_service_task(struct hclge_dev *hdev)\n {\n+\thclge_reset_subtask(hdev);\n \thclge_enable_vector(&hdev->misc_vector, true);\n }\n \n@@ -4498,6 +4703,7 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)\n \thdev->flag |= HCLGE_FLAG_USE_MSIX;\n \thdev->pdev = pdev;\n \thdev->ae_dev = ae_dev;\n+\thdev->reset_type = HNAE3_NONE_RESET;\n \tae_dev->priv = hdev;\n \n \tret = hclge_pci_init(hdev);\n@@ -4630,6 +4836,84 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)\n \treturn ret;\n }\n \n+static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)\n+{\n+\tstruct hclge_dev *hdev = ae_dev->priv;\n+\tstruct pci_dev *pdev = ae_dev->pdev;\n+\tint ret;\n+\n+\tset_bit(HCLGE_STATE_DOWN, &hdev->state);\n+\n+\tret = hclge_cmd_init(hdev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Cmd queue init failed\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = hclge_get_cap(hdev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"get hw capability error, ret = %d.\\n\",\n+\t\t\tret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hclge_configure(hdev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Configure dev error, ret = %d.\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hclge_map_tqp(hdev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Map tqp error, ret = %d.\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hclge_mac_init(hdev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Mac init error, ret = %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hclge_buffer_alloc(hdev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Buffer allocate fail, ret =%d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Enable tso fail, ret =%d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hclge_init_vlan_config(hdev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"VLAN init fail, ret =%d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hclge_tm_schd_init(hdev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"tm schd init fail, ret =%d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hclge_rss_init_hw(hdev);\n+\tif (ret) {\n+\t\tdev_err(&pdev->dev, \"Rss init fail, ret =%d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\t/* Enable MISC vector(vector0) */\n+\thclge_enable_vector(&hdev->misc_vector, true);\n+\n+\tdev_info(&pdev->dev, \"Reset done, %s driver initialization finished.\\n\",\n+\t\t HCLGE_DRIVER_NAME);\n+\n+\treturn 0;\n+}\n+\n static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)\n {\n \tstruct hclge_dev *hdev = ae_dev->priv;\n@@ -4699,6 +4983,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)\n \t.get_mdix_mode = hclge_get_mdix_mode,\n \t.set_vlan_filter = hclge_set_port_vlan_filter,\n \t.set_vf_vlan_filter = hclge_set_vf_vlan_filter,\n+\t.reset_event = hclge_reset_event,\n };\n \n static struct hnae3_ae_algo ae_algo = {\ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h\nindex 2a1d4d6..742e6ee 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h\n@@ -79,6 +79,19 @@\n #define HCLGE_PHY_MDIX_STATUS_B\t(6)\n #define HCLGE_PHY_SPEED_DUP_RESOLVE_B\t(11)\n \n+/* Reset related Registers */\n+#define HCLGE_MISC_RESET_STS_REG\t0x20700\n+#define HCLGE_GLOBAL_RESET_REG\t\t0x20A00\n+#define HCLGE_GLOBAL_RESET_BIT\t\t0x0\n+#define HCLGE_CORE_RESET_BIT\t\t0x1\n+#define HCLGE_FUN_RST_ING\t\t0x20C00\n+#define HCLGE_FUN_RST_ING_B\t\t0\n+\n+/* Vector0 register bits define */\n+#define HCLGE_VECTOR0_GLOBALRESET_INT_B\t5\n+#define HCLGE_VECTOR0_CORERESET_INT_B\t6\n+#define HCLGE_VECTOR0_IMPRESET_INT_B\t7\n+\n enum HCLGE_DEV_STATE {\n \tHCLGE_STATE_REINITING,\n \tHCLGE_STATE_DOWN,\n@@ -88,6 +101,7 @@ enum HCLGE_DEV_STATE {\n \tHCLGE_STATE_SERVICE_SCHED,\n \tHCLGE_STATE_MBX_HANDLING,\n \tHCLGE_STATE_MBX_IRQ,\n+\tHCLGE_STATE_RESET_INT,\n \tHCLGE_STATE_MAX\n };\n \n@@ -405,6 +419,7 @@ struct hclge_dev {\n \tstruct hclge_hw_stats hw_stats;\n \tunsigned long state;\n \n+\tenum hnae3_reset_type reset_type;\n \tu32 fw_version;\n \tu16 num_vmdq_vport;\t\t/* Num vmdq vport this PF has set up */\n \tu16 num_tqps;\t\t\t/* Num task queue pairs of this PF */\n", "prefixes": [ "V2", "net-next", "5/9" ] }