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{
    "id": 833239,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/833239/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20171102065626.21835-10-chunyan.zhang@spreadtrum.com/",
    "project": {
        "id": 37,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/37/?format=api",
        "name": "Devicetree Bindings",
        "link_name": "devicetree-bindings",
        "list_id": "devicetree.vger.kernel.org",
        "list_email": "devicetree@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20171102065626.21835-10-chunyan.zhang@spreadtrum.com>",
    "list_archive_url": null,
    "date": "2017-11-02T06:56:24",
    "name": "[V3,09/11] clk: sprd: add clocks support for SC9860",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "1d8c765e84b333d95b592634985fea32a9e66c37",
    "submitter": {
        "id": 64991,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/64991/?format=api",
        "name": "Chunyan Zhang",
        "email": "chunyan.zhang@spreadtrum.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20171102065626.21835-10-chunyan.zhang@spreadtrum.com/mbox/",
    "series": [
        {
            "id": 11448,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/11448/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=11448",
            "date": "2017-11-02T06:56:15",
            "name": "add clock driver for Spreadtrum platforms",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/11448/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/833239/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/833239/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<devicetree-owner@vger.kernel.org>",
        "X-Original-To": "incoming-dt@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3ySGRD5zY3z9t2V\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu,  2 Nov 2017 18:09:12 +1100 (AEDT)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752237AbdKBHJL (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tThu, 2 Nov 2017 03:09:11 -0400",
            "from sci-ig2.spreadtrum.com ([222.66.158.135]:61517 \"EHLO\n\tSHSQR01.spreadtrum.com\" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751841AbdKBHJK (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Thu, 2 Nov 2017 03:09:10 -0400",
            "from ig2.spreadtrum.com (shmbx03.spreadtrum.com [10.0.1.208])\n\tby SHSQR01.spreadtrum.com with ESMTP id vA2730gg017190\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO);\n\tThu, 2 Nov 2017 15:03:00 +0800 (CST)\n\t(envelope-from Chunyan.Zhang@spreadtrum.com)",
            "from SHCAS02.spreadtrum.com (10.0.1.202) by SHMBX03.spreadtrum.com\n\t(10.0.1.208) with Microsoft SMTP Server (TLS) id 15.0.847.32;\n\tThu, 2 Nov 2017 15:03:02 +0800",
            "from localhost (10.0.73.143) by SHCAS02.spreadtrum.com (10.0.1.250)\n\twith Microsoft SMTP Server (TLS) id 15.0.847.32 via Frontend\n\tTransport; Thu, 2 Nov 2017 15:03:01 +0800"
        ],
        "From": "Chunyan Zhang <chunyan.zhang@spreadtrum.com>",
        "To": "Stephen Boyd <sboyd@codeaurora.org>,\n\tMichael Turquette <mturquette@baylibre.com>,\n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>",
        "CC": "Catalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will.deacon@arm.com>, <linux-clk@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, Arnd Bergmann <arnd@arndb.de>,\n\tMark Brown <broonie@kernel.org>,\n\tXiaolong Zhang <xiaolong.zhang@spreadtrum.com>,\n\tBen Li <ben.li@spreadtrum.com>, <linux-arm-kernel@lists.infradead.org>,\n\t<linux-kernel@vger.kernel.org>, Orson Zhai <orson.zhai@spreadtrum.com>,\n\tChunyan Zhang <zhang.lyra@gmail.com>",
        "Subject": "[PATCH V3 09/11] clk: sprd: add clocks support for SC9860",
        "Date": "Thu, 2 Nov 2017 14:56:24 +0800",
        "Message-ID": "<20171102065626.21835-10-chunyan.zhang@spreadtrum.com>",
        "X-Mailer": "git-send-email 2.12.2",
        "In-Reply-To": "<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>",
        "References": "<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-MAIL": "SHSQR01.spreadtrum.com vA2730gg017190",
        "Sender": "devicetree-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<devicetree.vger.kernel.org>",
        "X-Mailing-List": "devicetree@vger.kernel.org"
    },
    "content": "This patch added the list of clocks for Spreadtrum's SC9860 SoC,\ntogether with clock initialization code.\n\nSigned-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>\n---\n drivers/clk/sprd/Kconfig                    |   10 +\n drivers/clk/sprd/Makefile                   |    3 +\n drivers/clk/sprd/sc9860-clk.c               | 1987 +++++++++++++++++++++++++++\n include/dt-bindings/clock/sprd,sc9860-clk.h |  408 ++++++\n 4 files changed, 2408 insertions(+)\n create mode 100644 drivers/clk/sprd/sc9860-clk.c\n create mode 100644 include/dt-bindings/clock/sprd,sc9860-clk.h",
    "diff": "diff --git a/drivers/clk/sprd/Kconfig b/drivers/clk/sprd/Kconfig\nindex 67a3287..8789247 100644\n--- a/drivers/clk/sprd/Kconfig\n+++ b/drivers/clk/sprd/Kconfig\n@@ -2,3 +2,13 @@ config SPRD_COMMON_CLK\n \ttristate \"Clock support for Spreadtrum SoCs\"\n \tdepends on ARCH_SPRD || COMPILE_TEST\n \tdefault ARCH_SPRD\n+\n+if SPRD_COMMON_CLK\n+\n+# SoC Drivers\n+\n+config SPRD_SC9860_CLK\n+\ttristate \"Support for the Spreadtrum SC9860 clocks\"\n+\tdepends on (ARM64 && ARCH_SPRD) || COMPILE_TEST\n+\tdefault ARM64 && ARCH_SPRD\n+endif\ndiff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\nindex d693969..b0d81e5 100644\n--- a/drivers/clk/sprd/Makefile\n+++ b/drivers/clk/sprd/Makefile\n@@ -6,3 +6,6 @@ clk-sprd-y\t+= mux.o\n clk-sprd-y\t+= div.o\n clk-sprd-y\t+= composite.o\n clk-sprd-y\t+= pll.o\n+\n+## SoC support\n+obj-$(CONFIG_SPRD_SC9860_CLK)\t+= sc9860-clk.o\ndiff --git a/drivers/clk/sprd/sc9860-clk.c b/drivers/clk/sprd/sc9860-clk.c\nnew file mode 100644\nindex 0000000..09e19ff\n--- /dev/null\n+++ b/drivers/clk/sprd/sc9860-clk.c\n@@ -0,0 +1,1987 @@\n+/*\n+ * Spreatrum SC9860 clock driver\n+ *\n+ * Copyright (C) 2017 Spreadtrum, Inc.\n+ * Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0\n+ */\n+\n+#include <linux/clk-provider.h>\n+#include <linux/err.h>\n+#include <linux/io.h>\n+#include <linux/module.h>\n+#include <linux/of_device.h>\n+#include <linux/platform_device.h>\n+#include <linux/slab.h>\n+\n+#include <dt-bindings/clock/sprd,sc9860-clk.h>\n+\n+#include \"common.h\"\n+#include \"composite.h\"\n+#include \"div.h\"\n+#include \"gate.h\"\n+#include \"mux.h\"\n+#include \"pll.h\"\n+\n+static CLK_FIXED_RATE(ext_rco_100m, \"ext-rco-100m\", 0, 100000000, 0);\n+static CLK_FIXED_RATE(ext_32k, \"ext-32k\", 0, 32768, 0);\n+\n+static CLK_FIXED_FACTOR(fac_4m,\t\t\"fac-4m\",\t\"ext-26m\",\n+\t\t\t6, 1, 0);\n+static CLK_FIXED_FACTOR(fac_2m,\t\t\"fac-2m\",\t\"ext-26m\",\n+\t\t\t13, 1, 0);\n+static CLK_FIXED_FACTOR(fac_1m,\t\t\"fac-1m\",\t\"ext-26m\",\n+\t\t\t26, 1, 0);\n+static CLK_FIXED_FACTOR(fac_250k,\t\"fac-250k\",\t\"ext-26m\",\n+\t\t\t104, 1, 0);\n+static CLK_FIXED_FACTOR(fac_rpll0_26m,\t\"rpll0-26m\",\t\"ext-26m\",\n+\t\t\t1, 1, 0);\n+static CLK_FIXED_FACTOR(fac_rpll1_26m,\t\"rpll1-26m\",\t\"ext-26m\",\n+\t\t\t1, 1, 0);\n+static CLK_FIXED_FACTOR(fac_rco_25m,\t\"rco-25m\",\t\"ext-rc0-100m\",\n+\t\t\t4, 1, 0);\n+static CLK_FIXED_FACTOR(fac_rco_4m,\t\"rco-4m\",\t\"ext-rc0-100m\",\n+\t\t\t25, 1, 0);\n+static CLK_FIXED_FACTOR(fac_rco_2m,\t\"rco-2m\",\t\"ext-rc0-100m\",\n+\t\t\t50, 1, 0);\n+static CLK_FIXED_FACTOR(fac_3k2,\t\"fac-3k2\",\t\"ext-32k\",\n+\t\t\t10, 1, 0);\n+static CLK_FIXED_FACTOR(fac_1k,\t\t\"fac-1k\",\t\"ext-32k\",\n+\t\t\t32, 1, 0);\n+\n+static SPRD_GATE_CLK(mpll0_gate,\t\"mpll0-gate\",\t\"ext-26m\", 0xb0,\n+\t\t     0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(mpll1_gate,\t\"mpll1-gate\",\t\"ext-26m\", 0xb0,\n+\t\t     0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(dpll0_gate,\t\"dpll0-gate\",\t\"ext-26m\", 0xb4,\n+\t\t     0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(dpll1_gate,\t\"dpll1-gate\",\t\"ext-26m\", 0xb4,\n+\t\t     0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ltepll0_gate,\t\"ltepll0-gate\",\t\"ext-26m\", 0xb8,\n+\t\t     0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(twpll_gate,\t\"twpll-gate\",\t\"ext-26m\", 0xbc,\n+\t\t     0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ltepll1_gate,\t\"ltepll1-gate\",\t\"ext-26m\", 0x10c,\n+\t\t     0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(rpll0_gate,\t\"rpll0-gate\",\t\"ext-26m\", 0x16c,\n+\t\t     0x1000, BIT(2), 0, 0);\n+static SPRD_GATE_CLK(rpll1_gate,\t\"rpll1-gate\",\t\"ext-26m\", 0x16c,\n+\t\t     0x1000, BIT(18), 0, 0);\n+static SPRD_GATE_CLK(cppll_gate,\t\"cppll-gate\",\t\"ext-26m\", 0x2b4,\n+\t\t     0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(gpll_gate,\t\t\"gpll-gate\",\t\"ext-26m\", 0x32c,\n+\t\t0x1000, BIT(0), CLK_IGNORE_UNUSED, CLK_GATE_SET_TO_DISABLE);\n+\n+static struct sprd_clk_common *sc9860_pmu_gate_clks[] = {\n+\t/* address base is 0x402b0000 */\n+\t&mpll0_gate.common,\n+\t&mpll1_gate.common,\n+\t&dpll0_gate.common,\n+\t&dpll1_gate.common,\n+\t&ltepll0_gate.common,\n+\t&twpll_gate.common,\n+\t&ltepll1_gate.common,\n+\t&rpll0_gate.common,\n+\t&rpll1_gate.common,\n+\t&cppll_gate.common,\n+\t&gpll_gate.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_pmu_gate_hws = {\n+\t.hws\t= {\n+\t\t[CLK_EXT_RCO_100M]\t= &ext_rco_100m.hw,\n+\t\t[CLK_EXT_32K]\t\t= &ext_32k.hw,\n+\t\t[CLK_FAC_4M]\t\t= &fac_4m.hw,\n+\t\t[CLK_FAC_2M]\t\t= &fac_2m.hw,\n+\t\t[CLK_FAC_1M]\t\t= &fac_1m.hw,\n+\t\t[CLK_FAC_250K]\t\t= &fac_250k.hw,\n+\t\t[CLK_FAC_RPLL0_26M]\t= &fac_rpll0_26m.hw,\n+\t\t[CLK_FAC_RPLL1_26M]\t= &fac_rpll1_26m.hw,\n+\t\t[CLK_FAC_RCO25M]\t= &fac_rco_25m.hw,\n+\t\t[CLK_FAC_RCO4M]\t\t= &fac_rco_4m.hw,\n+\t\t[CLK_FAC_RCO2M]\t\t= &fac_rco_2m.hw,\n+\t\t[CLK_FAC_3K2]\t\t= &fac_3k2.hw,\n+\t\t[CLK_FAC_1K]\t\t= &fac_1k.hw,\n+\t\t[CLK_MPLL0_GATE]\t= &mpll0_gate.common.hw,\n+\t\t[CLK_MPLL1_GATE]\t= &mpll1_gate.common.hw,\n+\t\t[CLK_DPLL0_GATE]\t= &dpll0_gate.common.hw,\n+\t\t[CLK_DPLL1_GATE]\t= &dpll1_gate.common.hw,\n+\t\t[CLK_LTEPLL0_GATE]\t= &ltepll0_gate.common.hw,\n+\t\t[CLK_TWPLL_GATE]\t= &twpll_gate.common.hw,\n+\t\t[CLK_LTEPLL1_GATE]\t= &ltepll1_gate.common.hw,\n+\t\t[CLK_RPLL0_GATE]\t= &rpll0_gate.common.hw,\n+\t\t[CLK_RPLL1_GATE]\t= &rpll1_gate.common.hw,\n+\t\t[CLK_CPPLL_GATE]\t= &cppll_gate.common.hw,\n+\t\t[CLK_GPLL_GATE]\t\t= &gpll_gate.common.hw,\n+\t},\n+\t.num\t= CLK_PMU_GATE_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_pmu_gate_desc = {\n+\t.clk_clks\t= sc9860_pmu_gate_clks,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_pmu_gate_clks),\n+\t.hw_clks        = &sc9860_pmu_gate_hws,\n+};\n+\n+/* GPLL/LPLL/DPLL/RPLL/CPLL */\n+static const u64 const itable1[4] = {3, 780000000, 988000000, 1196000000};\n+\n+/* TWPLL/MPLL0/MPLL1 */\n+static const u64 itable2[4] = {3, 1638000000, 2080000000, 2600000000UL};\n+\n+static const struct clk_bit_field const f_mpll0[PLL_FACT_MAX] = {\n+\t{ .shift = 20,\t.width = 1 },\t/* lock_done\t*/\n+\t{ .shift = 19,\t.width = 1 },\t/* div_s\t*/\n+\t{ .shift = 18,\t.width = 1 },\t/* mod_en\t*/\n+\t{ .shift = 17,\t.width = 1 },\t/* sdm_en\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* refin\t*/\n+\t{ .shift = 11,\t.width = 2 },\t/* ibias\t*/\n+\t{ .shift = 0,\t.width = 7 },\t/* n\t\t*/\n+\t{ .shift = 57,\t.width = 7 },\t/* nint\t\t*/\n+\t{ .shift = 32,\t.width = 23},\t/* kint\t\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* prediv\t*/\n+\t{ .shift = 56,\t.width = 1 },\t/* postdiv\t*/\n+};\n+static SPRD_PLL_WITH_ITABLE_K_FVCO(mpll0_clk, \"mpll0\", \"mpll0-gate\", 0x24,\n+\t\t\t\t   2, itable2, f_mpll0, 200,\n+\t\t\t\t   1000, 1000, 1, 1300000000);\n+\n+static const struct clk_bit_field const f_mpll1[PLL_FACT_MAX] = {\n+\t{ .shift = 20,\t.width = 1 },\t/* lock_done\t*/\n+\t{ .shift = 19,\t.width = 1 },\t/* div_s\t*/\n+\t{ .shift = 18,\t.width = 1 },\t/* mod_en\t*/\n+\t{ .shift = 17,\t.width = 1 },\t/* sdm_en\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* refin\t*/\n+\t{ .shift = 11,\t.width = 2 },\t/* ibias\t*/\n+\t{ .shift = 0,\t.width = 7 },\t/* n\t\t*/\n+\t{ .shift = 57,\t.width = 7 },\t/* nint\t\t*/\n+\t{ .shift = 32,\t.width = 23},\t/* kint\t\t*/\n+\t{ .shift = 56,\t.width = 1 },\t/* prediv\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* postdiv\t*/\n+};\n+static SPRD_PLL_WITH_ITABLE_1K(mpll1_clk, \"mpll1\", \"mpll1-gate\", 0x2c,\n+\t\t\t       2, itable2, f_mpll1, 200);\n+\n+static const struct clk_bit_field const f_dpll[PLL_FACT_MAX] = {\n+\t{ .shift = 16,\t.width = 1 },\t/* lock_done\t*/\n+\t{ .shift = 15,\t.width = 1 },\t/* div_s\t*/\n+\t{ .shift = 14,\t.width = 1 },\t/* mod_en\t*/\n+\t{ .shift = 13,\t.width = 1 },\t/* sdm_en\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* refin\t*/\n+\t{ .shift = 8,\t.width = 2 },\t/* ibias\t*/\n+\t{ .shift = 0,\t.width = 7 },\t/* n\t\t*/\n+\t{ .shift = 57,\t.width = 7 },\t/* nint\t\t*/\n+\t{ .shift = 32,\t.width = 23},\t/* kint\t\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* prediv\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* postdiv\t*/\n+};\n+static SPRD_PLL_WITH_ITABLE_1K(dpll0_clk, \"dpll0\", \"dpll0-gate\", 0x34,\n+\t\t\t       2, itable1, f_dpll, 200);\n+\n+static SPRD_PLL_WITH_ITABLE_1K(dpll1_clk, \"dpll1\", \"dpll1-gate\", 0x3c,\n+\t\t\t       2, itable1, f_dpll, 200);\n+\n+static const struct clk_bit_field const f_rpll[PLL_FACT_MAX] = {\n+\t{ .shift = 0,\t.width = 1 },\t/* lock_done\t*/\n+\t{ .shift = 3,\t.width = 1 },\t/* div_s\t*/\n+\t{ .shift = 80,\t.width = 1 },\t/* mod_en\t*/\n+\t{ .shift = 81,\t.width = 1 },\t/* sdm_en\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* refin\t*/\n+\t{ .shift = 14,\t.width = 2 },\t/* ibias\t*/\n+\t{ .shift = 16,\t.width = 7 },\t/* n\t\t*/\n+\t{ .shift = 4,\t.width = 7 },\t/* nint\t\t*/\n+\t{ .shift = 32,\t.width = 23},\t/* kint\t\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* prediv\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* postdiv\t*/\n+};\n+static SPRD_PLL_WITH_ITABLE_1K(rpll0_clk, \"rpll0\", \"rpll0-gate\", 0x44,\n+\t\t\t       3, itable1, f_rpll, 200);\n+\n+static SPRD_PLL_WITH_ITABLE_1K(rpll1_clk, \"rpll1\", \"rpll1-gate\", 0x50,\n+\t\t\t       3, itable1, f_rpll, 200);\n+\n+static const struct clk_bit_field const f_twpll[PLL_FACT_MAX] = {\n+\t{ .shift = 21,\t.width = 1 },\t/* lock_done\t*/\n+\t{ .shift = 20,\t.width = 1 },\t/* div_s\t*/\n+\t{ .shift = 19,\t.width = 1 },\t/* mod_en\t*/\n+\t{ .shift = 18,\t.width = 1 },\t/* sdm_en\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* refin\t*/\n+\t{ .shift = 13,\t.width = 2 },\t/* ibias\t*/\n+\t{ .shift = 0,\t.width = 7 },\t/* n\t\t*/\n+\t{ .shift = 57,\t.width = 7 },\t/* nint\t\t*/\n+\t{ .shift = 32,\t.width = 23},\t/* kint\t\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* prediv\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* postdiv\t*/\n+};\n+static SPRD_PLL_WITH_ITABLE_1K(twpll_clk, \"twpll\", \"twpll-gate\", 0x5c,\n+\t\t\t       2, itable2, f_twpll, 200);\n+\n+static const struct clk_bit_field const f_ltepll[PLL_FACT_MAX] = {\n+\t{ .shift = 31,\t.width = 1 },\t/* lock_done\t*/\n+\t{ .shift = 27,\t.width = 1 },\t/* div_s\t*/\n+\t{ .shift = 26,\t.width = 1 },\t/* mod_en\t*/\n+\t{ .shift = 25,\t.width = 1 },\t/* sdm_en\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* refin\t*/\n+\t{ .shift = 20,\t.width = 2 },\t/* ibias\t*/\n+\t{ .shift = 0,\t.width = 7 },\t/* n\t\t*/\n+\t{ .shift = 57,\t.width = 7 },\t/* nint\t\t*/\n+\t{ .shift = 32,\t.width = 23},\t/* kint\t\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* prediv\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* postdiv\t*/\n+};\n+static SPRD_PLL_WITH_ITABLE_1K(ltepll0_clk, \"ltepll0\", \"ltepll0-gate\",\n+\t\t\t       0x64, 2, itable1,\n+\t\t\t       f_ltepll, 200);\n+static SPRD_PLL_WITH_ITABLE_1K(ltepll1_clk, \"ltepll1\", \"ltepll1-gate\",\n+\t\t\t       0x6c, 2, itable1,\n+\t\t\t       f_ltepll, 200);\n+\n+static const struct clk_bit_field const f_gpll[PLL_FACT_MAX] = {\n+\t{ .shift = 18,\t.width = 1 },\t/* lock_done\t*/\n+\t{ .shift = 15,\t.width = 1 },\t/* div_s\t*/\n+\t{ .shift = 14,\t.width = 1 },\t/* mod_en\t*/\n+\t{ .shift = 13,\t.width = 1 },\t/* sdm_en\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* refin\t*/\n+\t{ .shift = 8,\t.width = 2 },\t/* ibias\t*/\n+\t{ .shift = 0,\t.width = 7 },\t/* n\t\t*/\n+\t{ .shift = 57,\t.width = 7 },\t/* nint\t\t*/\n+\t{ .shift = 32,\t.width = 23},\t/* kint\t\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* prediv\t*/\n+\t{ .shift = 17,\t.width = 1 },\t/* postdiv\t*/\n+};\n+static SPRD_PLL_WITH_ITABLE_K_FVCO(gpll_clk, \"gpll\", \"gpll-gate\", 0x9c,\n+\t\t\t\t   2, itable1, f_gpll, 200,\n+\t\t\t\t   1000, 1000, 1, 600000000);\n+\n+static const struct clk_bit_field const f_cppll[PLL_FACT_MAX] = {\n+\t{ .shift = 17,\t.width = 1 },\t/* lock_done\t*/\n+\t{ .shift = 15,\t.width = 1 },\t/* div_s\t*/\n+\t{ .shift = 14,\t.width = 1 },\t/* mod_en\t*/\n+\t{ .shift = 13,\t.width = 1 },\t/* sdm_en\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* refin\t*/\n+\t{ .shift = 8,\t.width = 2 },\t/* ibias\t*/\n+\t{ .shift = 0,\t.width = 7 },\t/* n\t\t*/\n+\t{ .shift = 57,\t.width = 7 },\t/* nint\t\t*/\n+\t{ .shift = 32,\t.width = 23},\t/* kint\t\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* prediv\t*/\n+\t{ .shift = 0,\t.width = 0 },\t/* postdiv\t*/\n+};\n+static SPRD_PLL_WITH_ITABLE_1K(cppll_clk, \"cppll\", \"cppll-gate\", 0xc4,\n+\t\t\t       2, itable1, f_cppll, 200);\n+\n+static CLK_FIXED_FACTOR(gpll_42m5, \"gpll-42m5\", \"gpll\", 20, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_768m, \"twpll-768m\", \"twpll\", 2, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_384m, \"twpll-384m\", \"twpll\", 4, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_192m, \"twpll-192m\", \"twpll\", 8, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_96m, \"twpll-96m\", \"twpll\", 16, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_48m, \"twpll-48m\", \"twpll\", 32, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_24m, \"twpll-24m\", \"twpll\", 64, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_12m, \"twpll-12m\", \"twpll\", 128, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_512m, \"twpll-512m\", \"twpll\", 3, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_256m, \"twpll-256m\", \"twpll\", 6, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_128m, \"twpll-128m\", \"twpll\", 12, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_64m, \"twpll-64m\", \"twpll\", 24, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_307m2, \"twpll-307m2\", \"twpll\", 5, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_153m6, \"twpll-153m6\", \"twpll\", 10, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_76m8, \"twpll-76m8\", \"twpll\", 20, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_51m2, \"twpll-51m2\", \"twpll\", 30, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_38m4, \"twpll-38m4\", \"twpll\", 40, 1, 0);\n+static CLK_FIXED_FACTOR(twpll_19m2, \"twpll-19m2\", \"twpll\", 80, 1, 0);\n+static CLK_FIXED_FACTOR(l0_614m4, \"l0-614m4\", \"ltepll0\", 2, 1, 0);\n+static CLK_FIXED_FACTOR(l0_409m6, \"l0-409m6\", \"ltepll0\", 3, 1, 0);\n+static CLK_FIXED_FACTOR(l0_38m, \"l0-38m\", \"ltepll0\", 32, 1, 0);\n+static CLK_FIXED_FACTOR(l1_38m, \"l1-38m\", \"ltepll1\", 32, 1, 0);\n+static CLK_FIXED_FACTOR(rpll0_192m, \"rpll0-192m\", \"rpll0\", 6, 1, 0);\n+static CLK_FIXED_FACTOR(rpll0_96m, \"rpll0-96m\", \"rpll0\", 12, 1, 0);\n+static CLK_FIXED_FACTOR(rpll0_48m, \"rpll0-48m\", \"rpll0\", 24, 1, 0);\n+static CLK_FIXED_FACTOR(rpll1_468m, \"rpll1-468m\", \"rpll1\", 2, 1, 0);\n+static CLK_FIXED_FACTOR(rpll1_192m, \"rpll1-192m\", \"rpll1\", 6, 1, 0);\n+static CLK_FIXED_FACTOR(rpll1_96m, \"rpll1-96m\", \"rpll1\", 12, 1, 0);\n+static CLK_FIXED_FACTOR(rpll1_64m, \"rpll1-64m\", \"rpll1\", 18, 1, 0);\n+static CLK_FIXED_FACTOR(rpll1_48m, \"rpll1-48m\", \"rpll1\", 24, 1, 0);\n+static CLK_FIXED_FACTOR(dpll0_50m, \"dpll0-50m\", \"dpll0\", 16, 1, 0);\n+static CLK_FIXED_FACTOR(dpll1_50m, \"dpll1-50m\", \"dpll1\", 16, 1, 0);\n+static CLK_FIXED_FACTOR(cppll_50m, \"cppll-50m\", \"cppll\", 18, 1, 0);\n+static CLK_FIXED_FACTOR(m0_39m, \"m0-39m\", \"mpll0\", 32, 1, 0);\n+static CLK_FIXED_FACTOR(m1_63m, \"m1-63m\", \"mpll1\", 32, 1, 0);\n+\n+static struct sprd_clk_common *sc9860_pll_clks[] = {\n+\t/* address base is 0x40400000 */\n+\t&mpll0_clk.common,\n+\t&mpll1_clk.common,\n+\t&dpll0_clk.common,\n+\t&dpll1_clk.common,\n+\t&rpll0_clk.common,\n+\t&rpll1_clk.common,\n+\t&twpll_clk.common,\n+\t&ltepll0_clk.common,\n+\t&ltepll1_clk.common,\n+\t&gpll_clk.common,\n+\t&cppll_clk.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_pll_hws = {\n+\t.hws\t= {\n+\t\t[CLK_MPLL0]\t\t= &mpll0_clk.common.hw,\n+\t\t[CLK_MPLL1]\t\t= &mpll1_clk.common.hw,\n+\t\t[CLK_DPLL0]\t\t= &dpll0_clk.common.hw,\n+\t\t[CLK_DPLL1]\t\t= &dpll1_clk.common.hw,\n+\t\t[CLK_RPLL0]\t\t= &rpll0_clk.common.hw,\n+\t\t[CLK_RPLL1]\t\t= &rpll1_clk.common.hw,\n+\t\t[CLK_TWPLL]\t\t= &twpll_clk.common.hw,\n+\t\t[CLK_LTEPLL0]\t\t= &ltepll0_clk.common.hw,\n+\t\t[CLK_LTEPLL1]\t\t= &ltepll1_clk.common.hw,\n+\t\t[CLK_GPLL]\t\t= &gpll_clk.common.hw,\n+\t\t[CLK_CPPLL]\t\t= &cppll_clk.common.hw,\n+\t\t[CLK_GPLL_42M5]\t\t= &gpll_42m5.hw,\n+\t\t[CLK_TWPLL_768M]\t= &twpll_768m.hw,\n+\t\t[CLK_TWPLL_384M]\t= &twpll_384m.hw,\n+\t\t[CLK_TWPLL_192M]\t= &twpll_192m.hw,\n+\t\t[CLK_TWPLL_96M]\t\t= &twpll_96m.hw,\n+\t\t[CLK_TWPLL_48M]\t\t= &twpll_48m.hw,\n+\t\t[CLK_TWPLL_24M]\t\t= &twpll_24m.hw,\n+\t\t[CLK_TWPLL_12M]\t\t= &twpll_12m.hw,\n+\t\t[CLK_TWPLL_512M]\t= &twpll_512m.hw,\n+\t\t[CLK_TWPLL_256M]\t= &twpll_256m.hw,\n+\t\t[CLK_TWPLL_128M]\t= &twpll_128m.hw,\n+\t\t[CLK_TWPLL_64M]\t\t= &twpll_64m.hw,\n+\t\t[CLK_TWPLL_307M2]\t= &twpll_307m2.hw,\n+\t\t[CLK_TWPLL_153M6]\t= &twpll_153m6.hw,\n+\t\t[CLK_TWPLL_76M8]\t= &twpll_76m8.hw,\n+\t\t[CLK_TWPLL_51M2]\t= &twpll_51m2.hw,\n+\t\t[CLK_TWPLL_38M4]\t= &twpll_38m4.hw,\n+\t\t[CLK_TWPLL_19M2]\t= &twpll_19m2.hw,\n+\t\t[CLK_L0_614M4]\t\t= &l0_614m4.hw,\n+\t\t[CLK_L0_409M6]\t\t= &l0_409m6.hw,\n+\t\t[CLK_L0_38M]\t\t= &l0_38m.hw,\n+\t\t[CLK_L1_38M]\t\t= &l1_38m.hw,\n+\t\t[CLK_RPLL0_192M]\t= &rpll0_192m.hw,\n+\t\t[CLK_RPLL0_96M]\t\t= &rpll0_96m.hw,\n+\t\t[CLK_RPLL0_48M]\t\t= &rpll0_48m.hw,\n+\t\t[CLK_RPLL1_468M]\t= &rpll1_468m.hw,\n+\t\t[CLK_RPLL1_192M]\t= &rpll1_192m.hw,\n+\t\t[CLK_RPLL1_96M]\t\t= &rpll1_96m.hw,\n+\t\t[CLK_RPLL1_64M]\t\t= &rpll1_64m.hw,\n+\t\t[CLK_RPLL1_48M]\t\t= &rpll1_48m.hw,\n+\t\t[CLK_DPLL0_50M]\t\t= &dpll0_50m.hw,\n+\t\t[CLK_DPLL1_50M]\t\t= &dpll1_50m.hw,\n+\t\t[CLK_CPPLL_50M]\t\t= &cppll_50m.hw,\n+\t\t[CLK_M0_39M]\t\t= &m0_39m.hw,\n+\t\t[CLK_M1_63M]\t\t= &m1_63m.hw,\n+\t},\n+\t.num\t= CLK_PLL_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_pll_desc = {\n+\t.clk_clks\t= sc9860_pll_clks,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_pll_clks),\n+\t.hw_clks\t= &sc9860_pll_hws,\n+};\n+\n+#define SC9860_MUX_FLAG\t\\\n+\t(CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT)\n+\n+static const char * const ap_apb_parents[] = { \"ext-26m\", \"twpll-64m\",\n+\t\t\t\t\t       \"twpll-96m\", \"twpll-128m\" };\n+static SPRD_MUX_CLK(ap_apb, \"ap-apb\", ap_apb_parents, NULL,\n+\t\t    0x20, 0, 1, SC9860_MUX_FLAG);\n+\n+static const char * const ap_apb_usb3[] = { \"ext-32k\", \"twpll-24m\" };\n+static SPRD_MUX_CLK(ap_usb3, \"ap-usb3\", ap_apb_usb3, NULL,\n+\t\t    0x2c, 0, 1, SC9860_MUX_FLAG);\n+\n+static const char * const uart_parents[] = {\t\"ext-26m\",\t\"twpll-48m\",\n+\t\t\t\t\t\t\"twpll-51m2\",\t\"twpll-96m\" };\n+static SPRD_COMP_CLK(uart0_clk,\t\"uart0\",\tuart_parents, 0x30,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(uart1_clk,\t\"uart1\",\tuart_parents, 0x34,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(uart2_clk,\t\"uart2\",\tuart_parents, 0x38,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(uart3_clk,\t\"uart3\",\tuart_parents, 0x3c,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(uart4_clk,\t\"uart4\",\tuart_parents, 0x40,\n+\t\t     0, 0, 2, 8, 3, 0);\n+\n+static const char * const i2c_parents[] = { \"ext-26m\", \"twpll-48m\",\n+\t\t\t\t\t    \"twpll-51m2\", \"twpll-153m6\" };\n+static SPRD_COMP_CLK(i2c0_clk,\t\"i2c0\", i2c_parents, 0x44,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(i2c1_clk,\t\"i2c1\", i2c_parents, 0x48,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(i2c2_clk,\t\"i2c2\", i2c_parents, 0x4c,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(i2c3_clk,\t\"i2c3\", i2c_parents, 0x50,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(i2c4_clk,\t\"i2c4\", i2c_parents, 0x54,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(i2c5_clk,\t\"i2c5\", i2c_parents, 0x58,\n+\t\t     0, 0, 2, 8, 3, 0);\n+\n+static const char * const spi_parents[] = {\t\"ext-26m\",\t\"twpll-128m\",\n+\t\t\t\t\t\t\"twpll-153m6\",\t\"twpll-192m\" };\n+static SPRD_COMP_CLK(spi0_clk,\t\"spi0\",\tspi_parents, 0x5c,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(spi1_clk,\t\"spi1\",\tspi_parents, 0x60,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(spi2_clk,\t\"spi2\",\tspi_parents, 0x64,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(spi3_clk,\t\"spi3\",\tspi_parents, 0x68,\n+\t\t     0, 0, 2, 8, 3, 0);\n+\n+static const char * const iis_parents[] = { \"ext-26m\",\n+\t\t\t\t\t    \"twpll-128m\",\n+\t\t\t\t\t    \"twpll-153m6\" };\n+static SPRD_COMP_CLK(iis0_clk,\t\"iis0\",\tiis_parents, 0x6c,\n+\t\t     0, 0, 2, 8, 6, 0);\n+static SPRD_COMP_CLK(iis1_clk,\t\"iis1\",\tiis_parents, 0x70,\n+\t\t     0, 0, 2, 8, 6, 0);\n+static SPRD_COMP_CLK(iis2_clk,\t\"iis2\",\tiis_parents, 0x74,\n+\t\t     0, 0, 2, 8, 6, 0);\n+static SPRD_COMP_CLK(iis3_clk,\t\"iis3\",\tiis_parents, 0x78,\n+\t\t     0, 0, 2, 8, 6, 0);\n+\n+static struct sprd_clk_common *sc9860_ap_clks[] = {\n+\t/* address base is 0x20000000 */\n+\t&ap_apb.common,\n+\t&ap_usb3.common,\n+\t&uart0_clk.common,\n+\t&uart1_clk.common,\n+\t&uart2_clk.common,\n+\t&uart3_clk.common,\n+\t&uart4_clk.common,\n+\t&i2c0_clk.common,\n+\t&i2c1_clk.common,\n+\t&i2c2_clk.common,\n+\t&i2c3_clk.common,\n+\t&i2c4_clk.common,\n+\t&i2c5_clk.common,\n+\t&spi0_clk.common,\n+\t&spi1_clk.common,\n+\t&spi2_clk.common,\n+\t&spi3_clk.common,\n+\t&iis0_clk.common,\n+\t&iis1_clk.common,\n+\t&iis2_clk.common,\n+\t&iis3_clk.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_ap_clk_hws = {\n+\t.hws\t= {\n+\t\t[CLK_AP_APB]\t= &ap_apb.common.hw,\n+\t\t[CLK_AP_USB3]\t= &ap_usb3.common.hw,\n+\t\t[CLK_UART0]\t= &uart0_clk.common.hw,\n+\t\t[CLK_UART1]\t= &uart1_clk.common.hw,\n+\t\t[CLK_UART2]\t= &uart2_clk.common.hw,\n+\t\t[CLK_UART3]\t= &uart3_clk.common.hw,\n+\t\t[CLK_UART4]\t= &uart4_clk.common.hw,\n+\t\t[CLK_I2C0]\t= &i2c0_clk.common.hw,\n+\t\t[CLK_I2C1]\t= &i2c1_clk.common.hw,\n+\t\t[CLK_I2C2]\t= &i2c2_clk.common.hw,\n+\t\t[CLK_I2C3]\t= &i2c3_clk.common.hw,\n+\t\t[CLK_I2C4]\t= &i2c4_clk.common.hw,\n+\t\t[CLK_I2C5]\t= &i2c5_clk.common.hw,\n+\t\t[CLK_SPI0]\t= &spi0_clk.common.hw,\n+\t\t[CLK_SPI1]\t= &spi1_clk.common.hw,\n+\t\t[CLK_SPI2]\t= &spi2_clk.common.hw,\n+\t\t[CLK_SPI3]\t= &spi3_clk.common.hw,\n+\t\t[CLK_IIS0]\t= &iis0_clk.common.hw,\n+\t\t[CLK_IIS1]\t= &iis1_clk.common.hw,\n+\t\t[CLK_IIS2]\t= &iis2_clk.common.hw,\n+\t\t[CLK_IIS3]\t= &iis3_clk.common.hw,\n+\t},\n+\t.num\t= CLK_AP_CLK_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_ap_clk_desc = {\n+\t.clk_clks\t= sc9860_ap_clks,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_ap_clks),\n+\t.hw_clks\t= &sc9860_ap_clk_hws,\n+};\n+\n+static const char * const aon_apb_parents[] = { \"rco-25m\",\t\"ext-26m\",\n+\t\t\t\t\t\t\"ext-rco-100m\",\t\"twpll-96m\",\n+\t\t\t\t\t\t\"twpll-128m\",\n+\t\t\t\t\t\t\"twpll-153m6\" };\n+static SPRD_COMP_CLK(aon_apb, \"aon-apb\", aon_apb_parents, 0x230,\n+\t\t     0,\t0, 3, 8, 2, 0);\n+\n+static const char * const aux_parents[] = { \"ext-32k\",\t\t\"rpll0-26m\",\n+\t\t\t\t\t    \"rpll1-26m\",\t\"ext-26m\",\n+\t\t\t\t\t    \"cppll-50m\",\t\"rco-25m\",\n+\t\t\t\t\t    \"dpll0-50m\",\t\"dpll1-50m\",\n+\t\t\t\t\t    \"gpll-42m5\",\t\"twpll-48m\",\n+\t\t\t\t\t    \"m0-39m\",\t\t\"m1-63m\",\n+\t\t\t\t\t    \"l0-38m\",\t\t\"l1-38m\" };\n+\n+static SPRD_COMP_CLK(aux0_clk,\t\"aux0\",\t\taux_parents, 0x238,\n+\t\t     0, 0, 5, 8, 4, 0);\n+static SPRD_COMP_CLK(aux1_clk,\t\"aux1\",\t\taux_parents, 0x23c,\n+\t\t     0, 0, 5, 8, 4, 0);\n+static SPRD_COMP_CLK(aux2_clk,\t\"aux2\",\t\taux_parents, 0x240,\n+\t\t     0, 0, 5, 8, 4, 0);\n+static SPRD_COMP_CLK(probe_clk,\t\"probe\",\taux_parents, 0x244,\n+\t\t     0, 0, 5, 8, 4, 0);\n+\n+static const char * const sp_ahb_parents[] = {\t\"rco-4m\",\t\"ext-26m\",\n+\t\t\t\t\t\t\"ext-rco-100m\",\t\"twpll-96m\",\n+\t\t\t\t\t\t\"twpll-128m\",\n+\t\t\t\t\t\t\"twpll-153m6\" };\n+static SPRD_COMP_CLK(sp_ahb,\t\"sp-ahb\",\tsp_ahb_parents, 0x2d0,\n+\t\t     0, 0, 3, 8, 2, 0);\n+\n+static const char * const cci_parents[] = {\t\"ext-26m\",\t\"twpll-384m\",\n+\t\t\t\t\t\t\"l0-614m4\",\t\"twpll-768m\" };\n+static SPRD_COMP_CLK(cci_clk,\t\"cci\",\t\tcci_parents, 0x300,\n+\t\t     0,\t0, 2, 8, 2, 0);\n+static SPRD_COMP_CLK(gic_clk,\t\"gic\",\t\tcci_parents, 0x304,\n+\t\t     0, 0, 2, 8, 2, 0);\n+static SPRD_COMP_CLK(cssys_clk,\t\"cssys\",\tcci_parents, 0x310,\n+\t\t     0, 0, 2, 8, 2, 0);\n+\n+static const char * const sdio_2x_parents[] = {\t\"fac-1m\",\t\"ext-26m\",\n+\t\t\t\t\t\t\"twpll-307m2\",\t\"twpll-384m\",\n+\t\t\t\t\t\t\"l0-409m6\" };\n+static SPRD_COMP_CLK(sdio0_2x,\t\"sdio0-2x\",\tsdio_2x_parents, 0x328,\n+\t\t     0, 0, 3, 8, 4, 0);\n+static SPRD_COMP_CLK(sdio1_2x,\t\"sdio1-2x\",\tsdio_2x_parents, 0x330,\n+\t\t     0, 0, 3, 8, 4, 0);\n+static SPRD_COMP_CLK(sdio2_2x,\t\"sdio2-2x\",\tsdio_2x_parents, 0x338,\n+\t\t     0, 0, 3, 8, 4, 0);\n+static SPRD_COMP_CLK(emmc_2x,\t\"emmc-2x\",\tsdio_2x_parents, 0x340,\n+\t\t     0, 0, 3, 8, 4, 0);\n+\n+static SPRD_DIV_CLK(sdio0_1x,\t\"sdio0-1x\",\t\"sdio0-2x\",\t0x32c,\n+\t\t    8, 1, 0);\n+static SPRD_DIV_CLK(sdio1_1x,\t\"sdio1-1x\",\t\"sdio1-2x\",\t0x334,\n+\t\t    8, 1, 0);\n+static SPRD_DIV_CLK(sdio2_1x,\t\"sdio2-1x\",\t\"sdio2-2x\",\t0x33c,\n+\t\t    8, 1, 0);\n+static SPRD_DIV_CLK(emmc_1x,\t\"emmc-1x\",\t\"emmc-2x\",\t0x344,\n+\t\t    8, 1, 0);\n+\n+static const char * const adi_parents[] = {\t\"rco-4m\",\t\"ext-26m\",\n+\t\t\t\t\t\t\"rco-25m\",\t\"twpll-38m4\",\n+\t\t\t\t\t\t\"twpll-51m2\" };\n+static SPRD_MUX_CLK(adi_clk,\t\"adi\",\tadi_parents, NULL, 0x234,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+\n+static const char * const pwm_parents[] = {\t\"ext-32k\",\t\"ext-26m\",\n+\t\t\t\t\t\t\"rco-4m\",\t\"rco-25m\",\n+\t\t\t\t\t\t\"twpll-48m\" };\n+static SPRD_MUX_CLK(pwm0_clk,\t\"pwm0\",\tpwm_parents, NULL, 0x248,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+static SPRD_MUX_CLK(pwm1_clk,\t\"pwm1\",\tpwm_parents, NULL, 0x24c,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+static SPRD_MUX_CLK(pwm2_clk,\t\"pwm2\",\tpwm_parents, NULL, 0x250,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+static SPRD_MUX_CLK(pwm3_clk,\t\"pwm3\",\tpwm_parents, NULL, 0x254,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+\n+static const char * const efuse_parents[] = { \"rco-25m\", \"ext-26m\" };\n+static SPRD_MUX_CLK(efuse_clk, \"efuse\", efuse_parents, NULL, 0x258,\n+\t\t    0, 1, SC9860_MUX_FLAG);\n+\n+static const char * const cm3_uart_parents[] = { \"rco-4m\",\t\"ext-26m\",\n+\t\t\t\t\t\t \"rco-100m\",\t\"twpll-48m\",\n+\t\t\t\t\t\t \"twpll-51m2\",\t\"twpll-96m\",\n+\t\t\t\t\t\t \"twpll-128m\" };\n+static SPRD_MUX_CLK(cm3_uart0, \"cm3-uart0\", cm3_uart_parents, NULL, 0x25c,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+static SPRD_MUX_CLK(cm3_uart1, \"cm3-uart1\", cm3_uart_parents, NULL, 0x260,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+\n+static const char * const thm_parents[] = { \"ext-32k\", \"fac-250k\" };\n+static SPRD_MUX_CLK(thm_clk,\t\"thm\",\tthm_parents, NULL, 0x270,\n+\t\t    0, 1, SC9860_MUX_FLAG);\n+\n+static const char * const cm3_i2c_parents[] = {\t\"rco-4m\",\n+\t\t\t\t\t\t\"ext-26m\",\n+\t\t\t\t\t\t\"rco-100m\",\n+\t\t\t\t\t\t\"twpll-48m\",\n+\t\t\t\t\t\t\"twpll-51m2\",\n+\t\t\t\t\t\t\"twpll-153m6\" };\n+static SPRD_MUX_CLK(cm3_i2c0, \"cm3-i2c0\", cm3_i2c_parents, NULL, 0x274,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+static SPRD_MUX_CLK(cm3_i2c1, \"cm3-i2c1\", cm3_i2c_parents, NULL, 0x278,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+static SPRD_MUX_CLK(aon_i2c, \"aon-i2c\",\tcm3_i2c_parents, NULL, 0x280,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+\n+static const char * const cm4_spi_parents[] = {\t\"ext-26m\",\t\"twpll-96m\",\n+\t\t\t\t\t\t\"rco-100m\",\t\"twpll-128m\",\n+\t\t\t\t\t\t\"twpll-153m6\",\t\"twpll-192m\" };\n+static SPRD_MUX_CLK(cm4_spi, \"cm4-spi\", cm4_spi_parents, NULL, 0x27c,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+\n+static SPRD_MUX_CLK(avs_clk, \"avs\", uart_parents, NULL, 0x284,\n+\t\t    0, 2, SC9860_MUX_FLAG);\n+\n+static const char * const ca53_dap_parents[] = { \"ext-26m\",\t\"rco-4m\",\n+\t\t\t\t\t\t \"rco-100m\",\t\"twpll-76m8\",\n+\t\t\t\t\t\t \"twpll-128m\",\t\"twpll-153m6\" };\n+static SPRD_MUX_CLK(ca53_dap, \"ca53-dap\", ca53_dap_parents, NULL, 0x288,\n+\t\t    0, 3, SC9860_MUX_FLAG);\n+\n+static const char * const ca53_ts_parents[] = {\t\"ext-32k\", \"ext-26m\",\n+\t\t\t\t\t\t\"clk-twpll-128m\",\n+\t\t\t\t\t\t\"clk-twpll-153m6\" };\n+static SPRD_MUX_CLK(ca53_ts, \"ca53-ts\", ca53_ts_parents, NULL, 0x290,\n+\t\t    0, 2, SC9860_MUX_FLAG);\n+\n+static const char * const djtag_tck_parents[] = { \"rco-4m\", \"ext-26m\" };\n+static SPRD_MUX_CLK(djtag_tck, \"djtag-tck\", djtag_tck_parents, NULL,\n+\t0x2c8, 0, 1, SC9860_MUX_FLAG);\n+\n+static const char * const pmu_parents[] = { \"ext-32k\", \"rco-4m\", \"clk-4m\" };\n+static SPRD_MUX_CLK(pmu_clk, \"pmu\", pmu_parents, NULL, 0x2e0,\n+\t\t    0, 2, SC9860_MUX_FLAG);\n+\n+static const char * const pmu_26m_parents[] = { \"rco-25m\", \"ext-26m\" };\n+static SPRD_MUX_CLK(pmu_26m, \"pmu-26m\", pmu_26m_parents, NULL,\n+\t\t    0x2e4, 0, 1, SC9860_MUX_FLAG);\n+\n+static const char * const debounce_parents[] = { \"ext-32k\", \"rco-4m\",\n+\t\t\t\t\t\t \"rco-25m\", \"ext-26m\" };\n+static SPRD_MUX_CLK(debounce_clk, \"debounce\", debounce_parents, NULL,\n+\t\t    0x2e8, 0, 2, SC9860_MUX_FLAG);\n+\n+static const char * const otg2_ref_parents[] = { \"twpll-12m\", \"twpll-24m\" };\n+static SPRD_MUX_CLK(otg2_ref, \"otg2-ref\", otg2_ref_parents, NULL,\n+\t\t    0x2f4, 0, 1, SC9860_MUX_FLAG);\n+\n+static const char * const usb3_ref_parents[] = { \"twpll-24m\", \"twpll-19m2\",\n+\t\t\t\t\t\t \"twpll-48m\" };\n+static SPRD_MUX_CLK(usb3_ref, \"usb3-ref\", usb3_ref_parents, NULL,\n+\t\t    0x2f8, 0, 2, SC9860_MUX_FLAG);\n+\n+static const char * const ap_axi_parents[] = { \"ext-26m\", \"twpll-76m8\",\n+\t\t\t\t\t       \"twpll-128m\", \"twpll-256m\" };\n+static SPRD_MUX_CLK(ap_axi, \"ap-axi\", ap_axi_parents, NULL,\n+\t\t    0x324, 0, 2, SC9860_MUX_FLAG);\n+\n+static struct sprd_clk_common *sc9860_aon_prediv[] = {\n+\t/* address base is 0x402d0000 */\n+\t&aon_apb.common,\n+\t&aux0_clk.common,\n+\t&aux1_clk.common,\n+\t&aux2_clk.common,\n+\t&probe_clk.common,\n+\t&sp_ahb.common,\n+\t&cci_clk.common,\n+\t&gic_clk.common,\n+\t&cssys_clk.common,\n+\t&sdio0_2x.common,\n+\t&sdio1_2x.common,\n+\t&sdio2_2x.common,\n+\t&emmc_2x.common,\n+\t&sdio0_1x.common,\n+\t&sdio1_1x.common,\n+\t&sdio2_1x.common,\n+\t&emmc_1x.common,\n+\t&adi_clk.common,\n+\t&pwm0_clk.common,\n+\t&pwm1_clk.common,\n+\t&pwm2_clk.common,\n+\t&pwm3_clk.common,\n+\t&efuse_clk.common,\n+\t&cm3_uart0.common,\n+\t&cm3_uart1.common,\n+\t&thm_clk.common,\n+\t&cm3_i2c0.common,\n+\t&cm3_i2c1.common,\n+\t&cm4_spi.common,\n+\t&aon_i2c.common,\n+\t&avs_clk.common,\n+\t&ca53_dap.common,\n+\t&ca53_ts.common,\n+\t&djtag_tck.common,\n+\t&pmu_clk.common,\n+\t&pmu_26m.common,\n+\t&debounce_clk.common,\n+\t&otg2_ref.common,\n+\t&usb3_ref.common,\n+\t&ap_axi.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_aon_prediv_hws = {\n+\t.hws\t= {\n+\t\t[CLK_AON_APB]\t\t= &aon_apb.common.hw,\n+\t\t[CLK_AUX0]\t\t= &aux0_clk.common.hw,\n+\t\t[CLK_AUX1]\t\t= &aux1_clk.common.hw,\n+\t\t[CLK_AUX2]\t\t= &aux2_clk.common.hw,\n+\t\t[CLK_PROBE]\t\t= &probe_clk.common.hw,\n+\t\t[CLK_SP_AHB]\t\t= &sp_ahb.common.hw,\n+\t\t[CLK_CCI]\t\t= &cci_clk.common.hw,\n+\t\t[CLK_GIC]\t\t= &gic_clk.common.hw,\n+\t\t[CLK_CSSYS]\t\t= &cssys_clk.common.hw,\n+\t\t[CLK_SDIO0_2X]\t\t= &sdio0_2x.common.hw,\n+\t\t[CLK_SDIO1_2X]\t\t= &sdio1_2x.common.hw,\n+\t\t[CLK_SDIO2_2X]\t\t= &sdio2_2x.common.hw,\n+\t\t[CLK_EMMC_2X]\t\t= &emmc_2x.common.hw,\n+\t\t[CLK_SDIO0_1X]\t\t= &sdio0_1x.common.hw,\n+\t\t[CLK_SDIO1_1X]\t\t= &sdio1_1x.common.hw,\n+\t\t[CLK_SDIO2_1X]\t\t= &sdio2_1x.common.hw,\n+\t\t[CLK_EMMC_1X]\t\t= &emmc_1x.common.hw,\n+\t\t[CLK_ADI]\t\t= &adi_clk.common.hw,\n+\t\t[CLK_PWM0]\t\t= &pwm0_clk.common.hw,\n+\t\t[CLK_PWM1]\t\t= &pwm1_clk.common.hw,\n+\t\t[CLK_PWM2]\t\t= &pwm2_clk.common.hw,\n+\t\t[CLK_PWM3]\t\t= &pwm3_clk.common.hw,\n+\t\t[CLK_EFUSE]\t\t= &efuse_clk.common.hw,\n+\t\t[CLK_CM3_UART0]\t\t= &cm3_uart0.common.hw,\n+\t\t[CLK_CM3_UART1]\t\t= &cm3_uart1.common.hw,\n+\t\t[CLK_THM]\t\t= &thm_clk.common.hw,\n+\t\t[CLK_CM3_I2C0]\t\t= &cm3_i2c0.common.hw,\n+\t\t[CLK_CM3_I2C1]\t\t= &cm3_i2c1.common.hw,\n+\t\t[CLK_CM4_SPI]\t\t= &cm4_spi.common.hw,\n+\t\t[CLK_AON_I2C]\t\t= &aon_i2c.common.hw,\n+\t\t[CLK_AVS]\t\t= &avs_clk.common.hw,\n+\t\t[CLK_CA53_DAP]\t\t= &ca53_dap.common.hw,\n+\t\t[CLK_CA53_TS]\t\t= &ca53_ts.common.hw,\n+\t\t[CLK_DJTAG_TCK]\t\t= &djtag_tck.common.hw,\n+\t\t[CLK_PMU]\t\t= &pmu_clk.common.hw,\n+\t\t[CLK_PMU_26M]\t\t= &pmu_26m.common.hw,\n+\t\t[CLK_DEBOUNCE]\t\t= &debounce_clk.common.hw,\n+\t\t[CLK_OTG2_REF]\t\t= &otg2_ref.common.hw,\n+\t\t[CLK_USB3_REF]\t\t= &usb3_ref.common.hw,\n+\t\t[CLK_AP_AXI]\t\t= &ap_axi.common.hw,\n+\t},\n+\t.num\t= CLK_AON_PREDIV_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_aon_prediv_desc = {\n+\t.clk_clks\t= sc9860_aon_prediv,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_aon_prediv),\n+\t.hw_clks\t= &sc9860_aon_prediv_hws,\n+};\n+\n+static SPRD_GATE_CLK(usb3_eb,\t\t\"usb3-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(usb3_suspend,\t\"usb3-suspend\", \"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(usb3_ref_eb,\t\"usb3-ref-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(dma_eb,\t\t\"dma-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(sdio0_eb,\t\t\"sdio0-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(sdio1_eb,\t\t\"sdio1-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(sdio2_eb,\t\t\"sdio2-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(emmc_eb,\t\t\"emmc-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(rom_eb,\t\t\"rom-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(busmon_eb,\t\t\"busmon-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(cc63s_eb,\t\t\"cc63s-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(cc63p_eb,\t\t\"cc63p-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ce0_eb,\t\t\"ce0-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ce1_eb,\t\t\"ce1-eb\",\t\"ap-axi\", 0x0,\n+\t\t     0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);\n+\n+static struct sprd_clk_common *sc9860_apahb_gate[] = {\n+\t/* address base is 0x20210000 */\n+\t&usb3_eb.common,\n+\t&usb3_suspend.common,\n+\t&usb3_ref_eb.common,\n+\t&dma_eb.common,\n+\t&sdio0_eb.common,\n+\t&sdio1_eb.common,\n+\t&sdio2_eb.common,\n+\t&emmc_eb.common,\n+\t&rom_eb.common,\n+\t&busmon_eb.common,\n+\t&cc63s_eb.common,\n+\t&cc63p_eb.common,\n+\t&ce0_eb.common,\n+\t&ce1_eb.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_apahb_gate_hws = {\n+\t.hws\t= {\n+\t\t[CLK_USB3_EB]\t\t= &usb3_eb.common.hw,\n+\t\t[CLK_USB3_SUSPEND_EB]\t= &usb3_suspend.common.hw,\n+\t\t[CLK_USB3_REF_EB]\t= &usb3_ref_eb.common.hw,\n+\t\t[CLK_DMA_EB]\t\t= &dma_eb.common.hw,\n+\t\t[CLK_SDIO0_EB]\t\t= &sdio0_eb.common.hw,\n+\t\t[CLK_SDIO1_EB]\t\t= &sdio1_eb.common.hw,\n+\t\t[CLK_SDIO2_EB]\t\t= &sdio2_eb.common.hw,\n+\t\t[CLK_EMMC_EB]\t\t= &emmc_eb.common.hw,\n+\t\t[CLK_ROM_EB]\t\t= &rom_eb.common.hw,\n+\t\t[CLK_BUSMON_EB]\t\t= &busmon_eb.common.hw,\n+\t\t[CLK_CC63S_EB]\t\t= &cc63s_eb.common.hw,\n+\t\t[CLK_CC63P_EB]\t\t= &cc63p_eb.common.hw,\n+\t\t[CLK_CE0_EB]\t\t= &ce0_eb.common.hw,\n+\t\t[CLK_CE1_EB]\t\t= &ce1_eb.common.hw,\n+\t},\n+\t.num\t= CLK_APAHB_GATE_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_apahb_gate_desc = {\n+\t.clk_clks\t= sc9860_apahb_gate,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_apahb_gate),\n+\t.hw_clks\t= &sc9860_apahb_gate_hws,\n+};\n+\n+static SPRD_GATE_CLK(avs_lit_eb,\t\"avs-lit-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(avs_big_eb,\t\"avs-big-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ap_intc5_eb,\t\"ap-intc5-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(gpio_eb,\t\t\"gpio-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(pwm0_eb,\t\t\"pwm0-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(pwm1_eb,\t\t\"pwm1-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(pwm2_eb,\t\t\"pwm2-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(pwm3_eb,\t\t\"pwm3-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(kpd_eb,\t\t\"kpd-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(aon_sys_eb,\t\"aon-sys-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ap_sys_eb,\t\"ap-sys-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(aon_tmr_eb,\t\"aon-tmr-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ap_tmr0_eb,\t\"ap-tmr0-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(efuse_eb,\t\"efuse-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(eic_eb,\t\t\"eic-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(pub1_reg_eb,\t\"pub1-reg-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(adi_eb,\t\t\"adi-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ap_intc0_eb,\t\"ap-intc0-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ap_intc1_eb,\t\"ap-intc1-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ap_intc2_eb,\t\"ap-intc2-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ap_intc3_eb,\t\"ap-intc3-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ap_intc4_eb,\t\"ap-intc4-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(splk_eb,\t\t\"splk-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(mspi_eb,\t\t\"mspi-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(pub0_reg_eb,\t\"pub0-reg-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(pin_eb,\t\t\"pin-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(aon_ckg_eb,\t\"aon-ckg-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(gpu_eb,\t\t\"gpu-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(apcpu_ts0_eb,\t\"apcpu-ts0-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(apcpu_ts1_eb,\t\"apcpu-ts1-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(dap_eb,\t\t\"dap-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(i2c_eb,\t\t\"i2c-eb\",\t\"aon-apb\", 0x0,\n+\t\t     0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(pmu_eb,\t\t\"pmu-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(thm_eb,\t\t\"thm-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(aux0_eb,\t\t\"aux0-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(aux1_eb,\t\t\"aux1-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(aux2_eb,\t\t\"aux2-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(probe_eb,\t\t\"probe-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(gpu0_avs_eb,\t\"gpu0-avs-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(gpu1_avs_eb,\t\"gpu1-avs-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(apcpu_wdg_eb,\t\"apcpu-wdg-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ap_tmr1_eb,\t\"ap-tmr1-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ap_tmr2_eb,\t\"ap-tmr2-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(disp_emc_eb,\t\"disp-emc-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(zip_emc_eb,\t\"zip-emc-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(gsp_emc_eb,\t\"gsp-emc-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(osc_aon_eb,\t\"osc-aon-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(lvds_trx_eb,\t\"lvds-trx-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(lvds_tcxo_eb,\t\"lvds-tcxo-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(mdar_eb,\t\t\"mdar-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(rtc4m0_cal_eb, \"rtc4m0-cal-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(rct100m_cal_eb, \"rct100m-cal-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(djtag_eb,\t\t\"djtag-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(mbox_eb,\t\t\"mbox-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(21), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(aon_dma_eb,\t\"aon-dma-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(22), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(dbg_emc_eb,\t\"dbg-emc-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(23), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(lvds_pll_div_en, \"lvds-pll-div-en\", \"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(24), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(def_eb,\t\t\"def-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(25), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(aon_apb_rsv0,\t\"aon-apb-rsv0\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(26), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(orp_jtag_eb,\t\"orp-jtag-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(27), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(vsp_eb,\t\t\"vsp-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(28), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(cam_eb,\t\t\"cam-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(29), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(disp_eb,\t\t\"disp-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(30), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(dbg_axi_if_eb, \"dbg-axi-if-eb\",\t\"aon-apb\", 0x4,\n+\t\t     0x1000, BIT(31), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(sdio0_2x_en,\t\"sdio0-2x-en\",\t\"aon-apb\", 0x13c,\n+\t\t\t       0x1000, BIT(2), 0, 0);\n+static SPRD_GATE_CLK(sdio1_2x_en,\t\"sdio1-2x-en\",\t\"aon-apb\", 0x13c,\n+\t\t\t       0x1000, BIT(4), 0, 0);\n+static SPRD_GATE_CLK(sdio2_2x_en,\t\"sdio2-2x-en\",\t\"aon-apb\", 0x13c,\n+\t\t\t       0x1000, BIT(6), 0, 0);\n+static SPRD_GATE_CLK(emmc_2x_en,\t\"emmc-2x-en\",\t\"aon-apb\", 0x13c,\n+\t\t\t       0x1000, BIT(9), 0, 0);\n+\n+static struct sprd_clk_common *sc9860_aon_gate[] = {\n+\t/* address base is 0x402e0000 */\n+\t&avs_lit_eb.common,\n+\t&avs_big_eb.common,\n+\t&ap_intc5_eb.common,\n+\t&gpio_eb.common,\n+\t&pwm0_eb.common,\n+\t&pwm1_eb.common,\n+\t&pwm2_eb.common,\n+\t&pwm3_eb.common,\n+\t&kpd_eb.common,\n+\t&aon_sys_eb.common,\n+\t&ap_sys_eb.common,\n+\t&aon_tmr_eb.common,\n+\t&ap_tmr0_eb.common,\n+\t&efuse_eb.common,\n+\t&eic_eb.common,\n+\t&pub1_reg_eb.common,\n+\t&adi_eb.common,\n+\t&ap_intc0_eb.common,\n+\t&ap_intc1_eb.common,\n+\t&ap_intc2_eb.common,\n+\t&ap_intc3_eb.common,\n+\t&ap_intc4_eb.common,\n+\t&splk_eb.common,\n+\t&mspi_eb.common,\n+\t&pub0_reg_eb.common,\n+\t&pin_eb.common,\n+\t&aon_ckg_eb.common,\n+\t&gpu_eb.common,\n+\t&apcpu_ts0_eb.common,\n+\t&apcpu_ts1_eb.common,\n+\t&dap_eb.common,\n+\t&i2c_eb.common,\n+\t&pmu_eb.common,\n+\t&thm_eb.common,\n+\t&aux0_eb.common,\n+\t&aux1_eb.common,\n+\t&aux2_eb.common,\n+\t&probe_eb.common,\n+\t&gpu0_avs_eb.common,\n+\t&gpu1_avs_eb.common,\n+\t&apcpu_wdg_eb.common,\n+\t&ap_tmr1_eb.common,\n+\t&ap_tmr2_eb.common,\n+\t&disp_emc_eb.common,\n+\t&zip_emc_eb.common,\n+\t&gsp_emc_eb.common,\n+\t&osc_aon_eb.common,\n+\t&lvds_trx_eb.common,\n+\t&lvds_tcxo_eb.common,\n+\t&mdar_eb.common,\n+\t&rtc4m0_cal_eb.common,\n+\t&rct100m_cal_eb.common,\n+\t&djtag_eb.common,\n+\t&mbox_eb.common,\n+\t&aon_dma_eb.common,\n+\t&dbg_emc_eb.common,\n+\t&lvds_pll_div_en.common,\n+\t&def_eb.common,\n+\t&aon_apb_rsv0.common,\n+\t&orp_jtag_eb.common,\n+\t&vsp_eb.common,\n+\t&cam_eb.common,\n+\t&disp_eb.common,\n+\t&dbg_axi_if_eb.common,\n+\t&sdio0_2x_en.common,\n+\t&sdio1_2x_en.common,\n+\t&sdio2_2x_en.common,\n+\t&emmc_2x_en.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_aon_gate_hws = {\n+\t.hws\t= {\n+\t\t[CLK_AVS_LIT_EB]\t= &avs_lit_eb.common.hw,\n+\t\t[CLK_AVS_BIG_EB]\t= &avs_big_eb.common.hw,\n+\t\t[CLK_AP_INTC5_EB]\t= &ap_intc5_eb.common.hw,\n+\t\t[CLK_GPIO_EB]\t\t= &gpio_eb.common.hw,\n+\t\t[CLK_PWM0_EB]\t\t= &pwm0_eb.common.hw,\n+\t\t[CLK_PWM1_EB]\t\t= &pwm1_eb.common.hw,\n+\t\t[CLK_PWM2_EB]\t\t= &pwm2_eb.common.hw,\n+\t\t[CLK_PWM3_EB]\t\t= &pwm3_eb.common.hw,\n+\t\t[CLK_KPD_EB]\t\t= &kpd_eb.common.hw,\n+\t\t[CLK_AON_SYS_EB]\t= &aon_sys_eb.common.hw,\n+\t\t[CLK_AP_SYS_EB]\t\t= &ap_sys_eb.common.hw,\n+\t\t[CLK_AON_TMR_EB]\t= &aon_tmr_eb.common.hw,\n+\t\t[CLK_AP_TMR0_EB]\t= &ap_tmr0_eb.common.hw,\n+\t\t[CLK_EFUSE_EB]\t\t= &efuse_eb.common.hw,\n+\t\t[CLK_EIC_EB]\t\t= &eic_eb.common.hw,\n+\t\t[CLK_PUB1_REG_EB]\t= &pub1_reg_eb.common.hw,\n+\t\t[CLK_ADI_EB]\t\t= &adi_eb.common.hw,\n+\t\t[CLK_AP_INTC0_EB]\t= &ap_intc0_eb.common.hw,\n+\t\t[CLK_AP_INTC1_EB]\t= &ap_intc1_eb.common.hw,\n+\t\t[CLK_AP_INTC2_EB]\t= &ap_intc2_eb.common.hw,\n+\t\t[CLK_AP_INTC3_EB]\t= &ap_intc3_eb.common.hw,\n+\t\t[CLK_AP_INTC4_EB]\t= &ap_intc4_eb.common.hw,\n+\t\t[CLK_SPLK_EB]\t\t= &splk_eb.common.hw,\n+\t\t[CLK_MSPI_EB]\t\t= &mspi_eb.common.hw,\n+\t\t[CLK_PUB0_REG_EB]\t= &pub0_reg_eb.common.hw,\n+\t\t[CLK_PIN_EB]\t\t= &pin_eb.common.hw,\n+\t\t[CLK_AON_CKG_EB]\t= &aon_ckg_eb.common.hw,\n+\t\t[CLK_GPU_EB]\t\t= &gpu_eb.common.hw,\n+\t\t[CLK_APCPU_TS0_EB]\t= &apcpu_ts0_eb.common.hw,\n+\t\t[CLK_APCPU_TS1_EB]\t= &apcpu_ts1_eb.common.hw,\n+\t\t[CLK_DAP_EB]\t\t= &dap_eb.common.hw,\n+\t\t[CLK_I2C_EB]\t\t= &i2c_eb.common.hw,\n+\t\t[CLK_PMU_EB]\t\t= &pmu_eb.common.hw,\n+\t\t[CLK_THM_EB]\t\t= &thm_eb.common.hw,\n+\t\t[CLK_AUX0_EB]\t\t= &aux0_eb.common.hw,\n+\t\t[CLK_AUX1_EB]\t\t= &aux1_eb.common.hw,\n+\t\t[CLK_AUX2_EB]\t\t= &aux2_eb.common.hw,\n+\t\t[CLK_PROBE_EB]\t\t= &probe_eb.common.hw,\n+\t\t[CLK_GPU0_AVS_EB]\t= &gpu0_avs_eb.common.hw,\n+\t\t[CLK_GPU1_AVS_EB]\t= &gpu1_avs_eb.common.hw,\n+\t\t[CLK_APCPU_WDG_EB]\t= &apcpu_wdg_eb.common.hw,\n+\t\t[CLK_AP_TMR1_EB]\t= &ap_tmr1_eb.common.hw,\n+\t\t[CLK_AP_TMR2_EB]\t= &ap_tmr2_eb.common.hw,\n+\t\t[CLK_DISP_EMC_EB]\t= &disp_emc_eb.common.hw,\n+\t\t[CLK_ZIP_EMC_EB]\t= &zip_emc_eb.common.hw,\n+\t\t[CLK_GSP_EMC_EB]\t= &gsp_emc_eb.common.hw,\n+\t\t[CLK_OSC_AON_EB]\t= &osc_aon_eb.common.hw,\n+\t\t[CLK_LVDS_TRX_EB]\t= &lvds_trx_eb.common.hw,\n+\t\t[CLK_LVDS_TCXO_EB]\t= &lvds_tcxo_eb.common.hw,\n+\t\t[CLK_MDAR_EB]\t\t= &mdar_eb.common.hw,\n+\t\t[CLK_RTC4M0_CAL_EB]\t= &rtc4m0_cal_eb.common.hw,\n+\t\t[CLK_RCT100M_CAL_EB]\t= &rct100m_cal_eb.common.hw,\n+\t\t[CLK_DJTAG_EB]\t\t= &djtag_eb.common.hw,\n+\t\t[CLK_MBOX_EB]\t\t= &mbox_eb.common.hw,\n+\t\t[CLK_AON_DMA_EB]\t= &aon_dma_eb.common.hw,\n+\t\t[CLK_DBG_EMC_EB]\t= &dbg_emc_eb.common.hw,\n+\t\t[CLK_LVDS_PLL_DIV_EN]\t= &lvds_pll_div_en.common.hw,\n+\t\t[CLK_DEF_EB]\t\t= &def_eb.common.hw,\n+\t\t[CLK_AON_APB_RSV0]\t= &aon_apb_rsv0.common.hw,\n+\t\t[CLK_ORP_JTAG_EB]\t= &orp_jtag_eb.common.hw,\n+\t\t[CLK_VSP_EB]\t\t= &vsp_eb.common.hw,\n+\t\t[CLK_CAM_EB]\t\t= &cam_eb.common.hw,\n+\t\t[CLK_DISP_EB]\t\t= &disp_eb.common.hw,\n+\t\t[CLK_DBG_AXI_IF_EB]\t= &dbg_axi_if_eb.common.hw,\n+\t\t[CLK_SDIO0_2X_EN]\t= &sdio0_2x_en.common.hw,\n+\t\t[CLK_SDIO1_2X_EN]\t= &sdio1_2x_en.common.hw,\n+\t\t[CLK_SDIO2_2X_EN]\t= &sdio2_2x_en.common.hw,\n+\t\t[CLK_EMMC_2X_EN]\t= &emmc_2x_en.common.hw,\n+\t},\n+\t.num\t= CLK_AON_GATE_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_aon_gate_desc = {\n+\t.clk_clks\t= sc9860_aon_gate,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_aon_gate),\n+\t.hw_clks\t= &sc9860_aon_gate_hws,\n+};\n+\n+static const u8 mcu_table[] = { 0, 1, 2, 3, 4, 8 };\n+static const char * const lit_mcu_parents[] = {\t\"ext-26m\",\t\"twpll-512m\",\n+\t\t\t\t\t\t\"twpll-768m\",\t\"ltepll0\",\n+\t\t\t\t\t\t\"twpll\",\t\"mpll0\" };\n+static SPRD_COMP_CLK(lit_mcu,\t\"lit-mcu\",\tlit_mcu_parents, 0x20,\n+\t\t     mcu_table, 0, 4, 4, 3, 0);\n+\n+static const char * const big_mcu_parents[] = {\t\"ext-26m\",\t\"twpll-512m\",\n+\t\t\t\t\t\t\"twpll-768m\",\t\"ltepll0\",\n+\t\t\t\t\t\t\"twpll\",\t\"mpll1\" };\n+static SPRD_COMP_CLK(big_mcu,\t\"big-mcu\",\tbig_mcu_parents, 0x24,\n+\t\t     mcu_table, 0, 4, 4, 3, 0);\n+\n+static struct sprd_clk_common *sc9860_aonsecure_clk[] = {\n+\t/* address base is 0x40880000 */\n+\t&lit_mcu.common,\n+\t&big_mcu.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_aonsecure_clk_hws = {\n+\t.hws\t= {\n+\t\t[CLK_LIT_MCU]\t\t= &lit_mcu.common.hw,\n+\t\t[CLK_BIG_MCU]\t\t= &big_mcu.common.hw,\n+\t},\n+\t.num\t= CLK_AONSECURE_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_aonsecure_clk_desc = {\n+\t.clk_clks\t= sc9860_aonsecure_clk,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_aonsecure_clk),\n+\t.hw_clks\t= &sc9860_aonsecure_clk_hws,\n+};\n+\n+static SPRD_GATE_CLK(agcp_iis0_eb,\t\"agcp-iis0-eb\",\t\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(0), 0, 0);\n+static SPRD_GATE_CLK(agcp_iis1_eb,\t\"agcp-iis1-eb\",\t\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(1), 0, 0);\n+static SPRD_GATE_CLK(agcp_iis2_eb,\t\"agcp-iis2-eb\",\t\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(2), 0, 0);\n+static SPRD_GATE_CLK(agcp_iis3_eb,\t\"agcp-iis3-eb\",\t\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(3), 0, 0);\n+static SPRD_GATE_CLK(agcp_uart_eb,\t\"agcp-uart-eb\",\t\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(4), 0, 0);\n+static SPRD_GATE_CLK(agcp_dmacp_eb,\t\"agcp-dmacp-eb\",\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(5), 0, 0);\n+static SPRD_GATE_CLK(agcp_dmaap_eb,\t\"agcp-dmaap-eb\",\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(6), 0, 0);\n+static SPRD_GATE_CLK(agcp_arc48k_eb,\t\"agcp-arc48k-eb\",\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(10), 0, 0);\n+static SPRD_GATE_CLK(agcp_src44p1k_eb,\t\"agcp-src44p1k-eb\",\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(11), 0, 0);\n+static SPRD_GATE_CLK(agcp_mcdt_eb,\t\"agcp-mcdt-eb\",\t\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(12), 0, 0);\n+static SPRD_GATE_CLK(agcp_vbcifd_eb,\t\"agcp-vbcifd-eb\",\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(13), 0, 0);\n+static SPRD_GATE_CLK(agcp_vbc_eb,\t\"agcp-vbc-eb\",\t\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(14), 0, 0);\n+static SPRD_GATE_CLK(agcp_spinlock_eb,\t\"agcp-spinlock-eb\",\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(15), 0, 0);\n+static SPRD_GATE_CLK(agcp_icu_eb,\t\"agcp-icu-eb\",\t\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(16), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(agcp_ap_ashb_eb,\t\"agcp-ap-ashb-eb\",\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(17), 0, 0);\n+static SPRD_GATE_CLK(agcp_cp_ashb_eb,\t\"agcp-cp-ashb-eb\",\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(18), 0, 0);\n+static SPRD_GATE_CLK(agcp_aud_eb,\t\"agcp-aud-eb\",\t\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(19), 0, 0);\n+static SPRD_GATE_CLK(agcp_audif_eb,\t\"agcp-audif-eb\",\t\"aon-apb\",\n+\t\t     0x0, 0x100, BIT(20), 0, 0);\n+\n+static struct sprd_clk_common *sc9860_agcp_gate[] = {\n+\t/* address base is 0x415e0000 */\n+\t&agcp_iis0_eb.common,\n+\t&agcp_iis1_eb.common,\n+\t&agcp_iis2_eb.common,\n+\t&agcp_iis3_eb.common,\n+\t&agcp_uart_eb.common,\n+\t&agcp_dmacp_eb.common,\n+\t&agcp_dmaap_eb.common,\n+\t&agcp_arc48k_eb.common,\n+\t&agcp_src44p1k_eb.common,\n+\t&agcp_mcdt_eb.common,\n+\t&agcp_vbcifd_eb.common,\n+\t&agcp_vbc_eb.common,\n+\t&agcp_spinlock_eb.common,\n+\t&agcp_icu_eb.common,\n+\t&agcp_ap_ashb_eb.common,\n+\t&agcp_cp_ashb_eb.common,\n+\t&agcp_aud_eb.common,\n+\t&agcp_audif_eb.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_agcp_gate_hws = {\n+\t.hws\t= {\n+\t\t[CLK_AGCP_IIS0_EB]\t= &agcp_iis0_eb.common.hw,\n+\t\t[CLK_AGCP_IIS1_EB]\t= &agcp_iis1_eb.common.hw,\n+\t\t[CLK_AGCP_IIS2_EB]\t= &agcp_iis2_eb.common.hw,\n+\t\t[CLK_AGCP_IIS3_EB]\t= &agcp_iis3_eb.common.hw,\n+\t\t[CLK_AGCP_UART_EB]\t= &agcp_uart_eb.common.hw,\n+\t\t[CLK_AGCP_DMACP_EB]\t= &agcp_dmacp_eb.common.hw,\n+\t\t[CLK_AGCP_DMAAP_EB]\t= &agcp_dmaap_eb.common.hw,\n+\t\t[CLK_AGCP_ARC48K_EB]\t= &agcp_arc48k_eb.common.hw,\n+\t\t[CLK_AGCP_SRC44P1K_EB]\t= &agcp_src44p1k_eb.common.hw,\n+\t\t[CLK_AGCP_MCDT_EB]\t= &agcp_mcdt_eb.common.hw,\n+\t\t[CLK_AGCP_VBCIFD_EB]\t= &agcp_vbcifd_eb.common.hw,\n+\t\t[CLK_AGCP_VBC_EB]\t= &agcp_vbc_eb.common.hw,\n+\t\t[CLK_AGCP_SPINLOCK_EB]\t= &agcp_spinlock_eb.common.hw,\n+\t\t[CLK_AGCP_ICU_EB]\t= &agcp_icu_eb.common.hw,\n+\t\t[CLK_AGCP_AP_ASHB_EB]\t= &agcp_ap_ashb_eb.common.hw,\n+\t\t[CLK_AGCP_CP_ASHB_EB]\t= &agcp_cp_ashb_eb.common.hw,\n+\t\t[CLK_AGCP_AUD_EB]\t= &agcp_aud_eb.common.hw,\n+\t\t[CLK_AGCP_AUDIF_EB]\t= &agcp_audif_eb.common.hw,\n+\t},\n+\t.num\t= CLK_AGCP_GATE_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_agcp_gate_desc = {\n+\t.clk_clks\t= sc9860_agcp_gate,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_agcp_gate),\n+\t.hw_clks\t= &sc9860_agcp_gate_hws,\n+};\n+\n+static const char * const gpu_parents[] = { \"twpll-512m\",\n+\t\t\t\t\t    \"twpll-768m\",\n+\t\t\t\t\t    \"gpll\" };\n+static SPRD_COMP_CLK(gpu_clk,\t\"gpu\",\tgpu_parents, 0x20,\n+\t\t     0, 0, 2, 8, 4, 0);\n+\n+static struct sprd_clk_common *sc9860_gpu_clk[] = {\n+\t/* address base is 0x60200000 */\n+\t&gpu_clk.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_gpu_clk_hws = {\n+\t.hws\t= {\n+\t\t[CLK_GPU]\t= &gpu_clk.common.hw,\n+\t},\n+\t.num\t= CLK_GPU_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_gpu_clk_desc = {\n+\t.clk_clks\t= sc9860_gpu_clk,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_gpu_clk),\n+\t.hw_clks\t= &sc9860_gpu_clk_hws,\n+};\n+\n+static const char * const ahb_parents[] = { \"ext-26m\", \"twpll-96m\",\n+\t\t\t\t\t    \"twpll-128m\", \"twpll-153m6\" };\n+static SPRD_MUX_CLK(ahb_vsp, \"ahb-vsp\", ahb_parents, NULL,\n+\t\t    0x20, 0, 2, SC9860_MUX_FLAG);\n+\n+static const char * const vsp_parents[] = {\t\"twpll-76m8\",\t\"twpll-128m\",\n+\t\t\t\t\t\t\"twpll-256m\",\t\"twpll-307m2\",\n+\t\t\t\t\t\t\"twpll-384m\" };\n+static SPRD_COMP_CLK(vsp_clk, \"vsp\", vsp_parents, 0x24, 0, 0, 3, 8, 2, 0);\n+\n+static const char * const dispc_parents[] = {\t\"twpll-76m8\",\t\"twpll-128m\",\n+\t\t\t\t\t\t\"twpll-256m\",\t\"twpll-307m2\" };\n+static SPRD_COMP_CLK(vsp_enc, \"vsp-enc\", dispc_parents, 0x28, 0, 0, 2, 8, 2, 0);\n+\n+static const char * const vpp_parents[] = { \"twpll-96m\", \"twpll-153m6\",\n+\t\t\t\t\t    \"twpll-192m\", \"twpll-256m\" };\n+static SPRD_MUX_CLK(vpp_clk, \"vpp\", vpp_parents, NULL, 0x2c,\n+\t\t    0, 2, SC9860_MUX_FLAG);\n+static const char * const vsp_26m_parents[] = { \"ext-26m\" };\n+static SPRD_MUX_CLK(vsp_26m, \"vsp-26m\", vsp_26m_parents, NULL, 0x30,\n+\t\t    0, 1, SC9860_MUX_FLAG);\n+\n+static struct sprd_clk_common *sc9860_vsp_clk[] = {\n+\t/* address base is 0x61000000 */\n+\t&ahb_vsp.common,\n+\t&vsp_clk.common,\n+\t&vsp_enc.common,\n+\t&vpp_clk.common,\n+\t&vsp_26m.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_vsp_clk_hws = {\n+\t.hws\t= {\n+\t\t[CLK_AHB_VSP]\t= &ahb_vsp.common.hw,\n+\t\t[CLK_VSP]\t= &vsp_clk.common.hw,\n+\t\t[CLK_VSP_ENC]\t= &vsp_enc.common.hw,\n+\t\t[CLK_VPP]\t= &vpp_clk.common.hw,\n+\t\t[CLK_VSP_26M]\t= &vsp_26m.common.hw,\n+\t},\n+\t.num\t= CLK_VSP_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_vsp_clk_desc = {\n+\t.clk_clks\t= sc9860_vsp_clk,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_vsp_clk),\n+\t.hw_clks\t= &sc9860_vsp_clk_hws,\n+};\n+\n+static SPRD_GATE_CLK(vsp_dec_eb,\t\"vsp-dec-eb\",\t\"ahb-vsp\", 0x0,\n+\t\t     0x1000, BIT(0), 0, 0);\n+static SPRD_GATE_CLK(vsp_ckg_eb,\t\"vsp-ckg-eb\",\t\"ahb-vsp\", 0x0,\n+\t\t     0x1000, BIT(1), 0, 0);\n+static SPRD_GATE_CLK(vsp_mmu_eb,\t\"vsp-mmu-eb\",\t\"ahb-vsp\", 0x0,\n+\t\t     0x1000, BIT(2), 0, 0);\n+static SPRD_GATE_CLK(vsp_enc_eb,\t\"vsp-enc-eb\",\t\"ahb-vsp\", 0x0,\n+\t\t     0x1000, BIT(3), 0, 0);\n+static SPRD_GATE_CLK(vpp_eb,\t\t\"vpp-eb\",\t\"ahb-vsp\", 0x0,\n+\t\t     0x1000, BIT(4), 0, 0);\n+static SPRD_GATE_CLK(vsp_26m_eb,\t\"vsp-26m-eb\",\t\"ahb-vsp\", 0x0,\n+\t\t     0x1000, BIT(5), 0, 0);\n+static SPRD_GATE_CLK(vsp_axi_gate,\t\"vsp-axi-gate\",\t\"ahb-vsp\", 0x8,\n+\t\t     0, BIT(0), 0, 0);\n+static SPRD_GATE_CLK(vsp_enc_gate,\t\"vsp-enc-gate\",\t\"ahb-vsp\", 0x8,\n+\t\t     0, BIT(1), 0, 0);\n+static SPRD_GATE_CLK(vpp_axi_gate,\t\"vpp-axi-gate\",\t\"ahb-vsp\", 0x8,\n+\t\t     0, BIT(2), 0, 0);\n+static SPRD_GATE_CLK(vsp_bm_gate,\t\"vsp-bm-gate\",\t\"ahb-vsp\", 0x8,\n+\t\t     0, BIT(8), 0, 0);\n+static SPRD_GATE_CLK(vsp_enc_bm_gate, \"vsp-enc-bm-gate\", \"ahb-vsp\", 0x8,\n+\t\t     0, BIT(9), 0, 0);\n+static SPRD_GATE_CLK(vpp_bm_gate,\t\"vpp-bm-gate\",\t\"ahb-vsp\", 0x8,\n+\t\t     0, BIT(10), 0, 0);\n+\n+static struct sprd_clk_common *sc9860_vsp_gate[] = {\n+\t/* address base is 0x61100000 */\n+\t&vsp_dec_eb.common,\n+\t&vsp_ckg_eb.common,\n+\t&vsp_mmu_eb.common,\n+\t&vsp_enc_eb.common,\n+\t&vpp_eb.common,\n+\t&vsp_26m_eb.common,\n+\t&vsp_axi_gate.common,\n+\t&vsp_enc_gate.common,\n+\t&vpp_axi_gate.common,\n+\t&vsp_bm_gate.common,\n+\t&vsp_enc_bm_gate.common,\n+\t&vpp_bm_gate.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_vsp_gate_hws = {\n+\t.hws\t= {\n+\t\t[CLK_VSP_DEC_EB]\t= &vsp_dec_eb.common.hw,\n+\t\t[CLK_VSP_CKG_EB]\t= &vsp_ckg_eb.common.hw,\n+\t\t[CLK_VSP_MMU_EB]\t= &vsp_mmu_eb.common.hw,\n+\t\t[CLK_VSP_ENC_EB]\t= &vsp_enc_eb.common.hw,\n+\t\t[CLK_VPP_EB]\t\t= &vpp_eb.common.hw,\n+\t\t[CLK_VSP_26M_EB]\t= &vsp_26m_eb.common.hw,\n+\t\t[CLK_VSP_AXI_GATE]\t= &vsp_axi_gate.common.hw,\n+\t\t[CLK_VSP_ENC_GATE]\t= &vsp_enc_gate.common.hw,\n+\t\t[CLK_VPP_AXI_GATE]\t= &vpp_axi_gate.common.hw,\n+\t\t[CLK_VSP_BM_GATE]\t= &vsp_bm_gate.common.hw,\n+\t\t[CLK_VSP_ENC_BM_GATE]\t= &vsp_enc_bm_gate.common.hw,\n+\t\t[CLK_VPP_BM_GATE]\t= &vpp_bm_gate.common.hw,\n+\t},\n+\t.num\t= CLK_VSP_GATE_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_vsp_gate_desc = {\n+\t.clk_clks\t= sc9860_vsp_gate,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_vsp_gate),\n+\t.hw_clks\t= &sc9860_vsp_gate_hws,\n+};\n+\n+static SPRD_MUX_CLK(ahb_cam, \"ahb-cam\", ahb_parents, NULL,\n+\t\t    0x20, 0, 2, SC9860_MUX_FLAG);\n+static const char * const sensor_parents[] = {\t\"ext-26m\",\t\"twpll-48m\",\n+\t\t\t\t\t\t\"twpll-76m8\",\t\"twpll-96m\" };\n+static SPRD_COMP_CLK(sensor0_clk, \"sensor0\", sensor_parents, 0x24,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(sensor1_clk, \"sensor1\", sensor_parents, 0x28,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_COMP_CLK(sensor2_clk, \"sensor2\", sensor_parents, 0x2c,\n+\t\t     0, 0, 2, 8, 3, 0);\n+static SPRD_GATE_CLK(mipi_csi0_eb, \"mipi-csi0-eb\", \"ahb-cam\", 0x4c,\n+\t\t     0, BIT(16), 0, 0);\n+static SPRD_GATE_CLK(mipi_csi1_eb, \"mipi-csi1-eb\", \"ahb-cam\", 0x50,\n+\t\t     0, BIT(16), 0, 0);\n+\n+static struct sprd_clk_common *sc9860_cam_clk[] = {\n+\t/* address base is 0x62000000 */\n+\t&ahb_cam.common,\n+\t&sensor0_clk.common,\n+\t&sensor1_clk.common,\n+\t&sensor2_clk.common,\n+\t&mipi_csi0_eb.common,\n+\t&mipi_csi1_eb.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_cam_clk_hws = {\n+\t.hws\t= {\n+\t\t[CLK_AHB_CAM]\t\t= &ahb_cam.common.hw,\n+\t\t[CLK_SENSOR0]\t\t= &sensor0_clk.common.hw,\n+\t\t[CLK_SENSOR1]\t\t= &sensor1_clk.common.hw,\n+\t\t[CLK_SENSOR2]\t\t= &sensor2_clk.common.hw,\n+\t\t[CLK_MIPI_CSI0_EB]\t= &mipi_csi0_eb.common.hw,\n+\t\t[CLK_MIPI_CSI1_EB]\t= &mipi_csi1_eb.common.hw,\n+\t},\n+\t.num\t= CLK_CAM_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_cam_clk_desc = {\n+\t.clk_clks\t= sc9860_cam_clk,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_cam_clk),\n+\t.hw_clks\t= &sc9860_cam_clk_hws,\n+};\n+\n+static SPRD_GATE_CLK(dcam0_eb,\t\t\"dcam0-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(0), 0, 0);\n+static SPRD_GATE_CLK(dcam1_eb,\t\t\"dcam1-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(1), 0, 0);\n+static SPRD_GATE_CLK(isp0_eb,\t\t\"isp0-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(2), 0, 0);\n+static SPRD_GATE_CLK(csi0_eb,\t\t\"csi0-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(3), 0, 0);\n+static SPRD_GATE_CLK(csi1_eb,\t\t\"csi1-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(4), 0, 0);\n+static SPRD_GATE_CLK(jpg0_eb,\t\t\"jpg0-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(5), 0, 0);\n+static SPRD_GATE_CLK(jpg1_eb,\t\t\"jpg1-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(6), 0, 0);\n+static SPRD_GATE_CLK(cam_ckg_eb,\t\"cam-ckg-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(7), 0, 0);\n+static SPRD_GATE_CLK(cam_mmu_eb,\t\"cam-mmu-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(8), 0, 0);\n+static SPRD_GATE_CLK(isp1_eb,\t\t\"isp1-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(9), 0, 0);\n+static SPRD_GATE_CLK(cpp_eb,\t\t\"cpp-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(10), 0, 0);\n+static SPRD_GATE_CLK(mmu_pf_eb,\t\t\"mmu-pf-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(11), 0, 0);\n+static SPRD_GATE_CLK(isp2_eb,\t\t\"isp2-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(12), 0, 0);\n+static SPRD_GATE_CLK(dcam2isp_if_eb, \"dcam2isp-if-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(13), 0, 0);\n+static SPRD_GATE_CLK(isp2dcam_if_eb, \"isp2dcam-if-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(14), 0, 0);\n+static SPRD_GATE_CLK(isp_lclk_eb,\t\"isp-lclk-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(15), 0, 0);\n+static SPRD_GATE_CLK(isp_iclk_eb,\t\"isp-iclk-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(16), 0, 0);\n+static SPRD_GATE_CLK(isp_mclk_eb,\t\"isp-mclk-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(17), 0, 0);\n+static SPRD_GATE_CLK(isp_pclk_eb,\t\"isp-pclk-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(18), 0, 0);\n+static SPRD_GATE_CLK(isp_isp2dcam_eb, \"isp-isp2dcam-eb\", \"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(19), 0, 0);\n+static SPRD_GATE_CLK(dcam0_if_eb,\t\"dcam0-if-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(20), 0, 0);\n+static SPRD_GATE_CLK(clk26m_if_eb,\t\"clk26m-if-eb\",\t\"ahb-cam\", 0x0,\n+\t\t     0x1000, BIT(21), 0, 0);\n+static SPRD_GATE_CLK(cphy0_gate, \"cphy0-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(0), 0, 0);\n+static SPRD_GATE_CLK(mipi_csi0_gate, \"mipi-csi0-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(1), 0, 0);\n+static SPRD_GATE_CLK(cphy1_gate,\t\"cphy1-gate\",\t\"ahb-cam\", 0x8,\n+\t\t     0, BIT(2), 0, 0);\n+static SPRD_GATE_CLK(mipi_csi1,\t\t\"mipi-csi1\",\t\"ahb-cam\", 0x8,\n+\t\t     0, BIT(3), 0, 0);\n+static SPRD_GATE_CLK(dcam0_axi_gate,\t\"dcam0-axi-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(4), 0, 0);\n+static SPRD_GATE_CLK(dcam1_axi_gate,\t\"dcam1-axi-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(5), 0, 0);\n+static SPRD_GATE_CLK(sensor0_gate,\t\"sensor0-gate\",\t\"ahb-cam\", 0x8,\n+\t\t     0, BIT(6), 0, 0);\n+static SPRD_GATE_CLK(sensor1_gate,\t\"sensor1-gate\",\t\"ahb-cam\", 0x8,\n+\t\t     0, BIT(7), 0, 0);\n+static SPRD_GATE_CLK(jpg0_axi_gate,\t\"jpg0-axi-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(8), 0, 0);\n+static SPRD_GATE_CLK(gpg1_axi_gate,\t\"gpg1-axi-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(9), 0, 0);\n+static SPRD_GATE_CLK(isp0_axi_gate,\t\"isp0-axi-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(10), 0, 0);\n+static SPRD_GATE_CLK(isp1_axi_gate,\t\"isp1-axi-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(11), 0, 0);\n+static SPRD_GATE_CLK(isp2_axi_gate,\t\"isp2-axi-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(12), 0, 0);\n+static SPRD_GATE_CLK(cpp_axi_gate,\t\"cpp-axi-gate\",\t\"ahb-cam\", 0x8,\n+\t\t     0, BIT(13), 0, 0);\n+static SPRD_GATE_CLK(d0_if_axi_gate,\t\"d0-if-axi-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(14), 0, 0);\n+static SPRD_GATE_CLK(d2i_if_axi_gate, \"d2i-if-axi-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(15), 0, 0);\n+static SPRD_GATE_CLK(i2d_if_axi_gate, \"i2d-if-axi-gate\", \"ahb-cam\", 0x8,\n+\t\t     0, BIT(16), 0, 0);\n+static SPRD_GATE_CLK(spare_axi_gate, \"spare-axi-gate\",\t\"ahb-cam\", 0x8,\n+\t\t     0, BIT(17), 0, 0);\n+static SPRD_GATE_CLK(sensor2_gate, \"sensor2-gate\",\t\"ahb-cam\", 0x8,\n+\t\t     0, BIT(18), 0, 0);\n+static SPRD_GATE_CLK(d0if_in_d_en, \"d0if-in-d-en\", \"ahb-cam\", 0x28,\n+\t\t     0x1000, BIT(0), 0, 0);\n+static SPRD_GATE_CLK(d1if_in_d_en, \"d1if-in-d-en\", \"ahb-cam\", 0x28,\n+\t\t     0x1000, BIT(1), 0, 0);\n+static SPRD_GATE_CLK(d0if_in_d2i_en, \"d0if-in-d2i-en\", \"ahb-cam\", 0x28,\n+\t\t     0x1000, BIT(2), 0, 0);\n+static SPRD_GATE_CLK(d1if_in_d2i_en, \"d1if-in-d2i-en\",\t\"ahb-cam\", 0x28,\n+\t\t     0x1000, BIT(3), 0, 0);\n+static SPRD_GATE_CLK(ia_in_d2i_en, \"ia-in-d2i-en\",\t\"ahb-cam\", 0x28,\n+\t\t     0x1000, BIT(4), 0, 0);\n+static SPRD_GATE_CLK(ib_in_d2i_en,\t\"ib-in-d2i-en\",\t\"ahb-cam\", 0x28,\n+\t\t     0x1000, BIT(5), 0, 0);\n+static SPRD_GATE_CLK(ic_in_d2i_en,\t\"ic-in-d2i-en\",\t\"ahb-cam\", 0x28,\n+\t\t     0x1000, BIT(6), 0, 0);\n+static SPRD_GATE_CLK(ia_in_i_en,\t\"ia-in-i-en\",\t\"ahb-cam\", 0x28,\n+\t\t     0x1000, BIT(7), 0, 0);\n+static SPRD_GATE_CLK(ib_in_i_en,\t\"ib-in-i-en\",\t\"ahb-cam\", 0x28,\n+\t\t     0x1000, BIT(8), 0, 0);\n+static SPRD_GATE_CLK(ic_in_i_en,\t\"ic-in-i-en\",\t\"ahb-cam\", 0x28,\n+\t\t     0x1000, BIT(9), 0, 0);\n+\n+static struct sprd_clk_common *sc9860_cam_gate[] = {\n+\t/* address base is 0x62100000 */\n+\t&dcam0_eb.common,\n+\t&dcam1_eb.common,\n+\t&isp0_eb.common,\n+\t&csi0_eb.common,\n+\t&csi1_eb.common,\n+\t&jpg0_eb.common,\n+\t&jpg1_eb.common,\n+\t&cam_ckg_eb.common,\n+\t&cam_mmu_eb.common,\n+\t&isp1_eb.common,\n+\t&cpp_eb.common,\n+\t&mmu_pf_eb.common,\n+\t&isp2_eb.common,\n+\t&dcam2isp_if_eb.common,\n+\t&isp2dcam_if_eb.common,\n+\t&isp_lclk_eb.common,\n+\t&isp_iclk_eb.common,\n+\t&isp_mclk_eb.common,\n+\t&isp_pclk_eb.common,\n+\t&isp_isp2dcam_eb.common,\n+\t&dcam0_if_eb.common,\n+\t&clk26m_if_eb.common,\n+\t&cphy0_gate.common,\n+\t&mipi_csi0_gate.common,\n+\t&cphy1_gate.common,\n+\t&mipi_csi1.common,\n+\t&dcam0_axi_gate.common,\n+\t&dcam1_axi_gate.common,\n+\t&sensor0_gate.common,\n+\t&sensor1_gate.common,\n+\t&jpg0_axi_gate.common,\n+\t&gpg1_axi_gate.common,\n+\t&isp0_axi_gate.common,\n+\t&isp1_axi_gate.common,\n+\t&isp2_axi_gate.common,\n+\t&cpp_axi_gate.common,\n+\t&d0_if_axi_gate.common,\n+\t&d2i_if_axi_gate.common,\n+\t&i2d_if_axi_gate.common,\n+\t&spare_axi_gate.common,\n+\t&sensor2_gate.common,\n+\t&d0if_in_d_en.common,\n+\t&d1if_in_d_en.common,\n+\t&d0if_in_d2i_en.common,\n+\t&d1if_in_d2i_en.common,\n+\t&ia_in_d2i_en.common,\n+\t&ib_in_d2i_en.common,\n+\t&ic_in_d2i_en.common,\n+\t&ia_in_i_en.common,\n+\t&ib_in_i_en.common,\n+\t&ic_in_i_en.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_cam_gate_hws = {\n+\t.hws\t= {\n+\t\t[CLK_DCAM0_EB]\t\t= &dcam0_eb.common.hw,\n+\t\t[CLK_DCAM1_EB]\t\t= &dcam1_eb.common.hw,\n+\t\t[CLK_ISP0_EB]\t\t= &isp0_eb.common.hw,\n+\t\t[CLK_CSI0_EB]\t\t= &csi0_eb.common.hw,\n+\t\t[CLK_CSI1_EB]\t\t= &csi1_eb.common.hw,\n+\t\t[CLK_JPG0_EB]\t\t= &jpg0_eb.common.hw,\n+\t\t[CLK_JPG1_EB]\t\t= &jpg1_eb.common.hw,\n+\t\t[CLK_CAM_CKG_EB]\t= &cam_ckg_eb.common.hw,\n+\t\t[CLK_CAM_MMU_EB]\t= &cam_mmu_eb.common.hw,\n+\t\t[CLK_ISP1_EB]\t\t= &isp1_eb.common.hw,\n+\t\t[CLK_CPP_EB]\t\t= &cpp_eb.common.hw,\n+\t\t[CLK_MMU_PF_EB]\t\t= &mmu_pf_eb.common.hw,\n+\t\t[CLK_ISP2_EB]\t\t= &isp2_eb.common.hw,\n+\t\t[CLK_DCAM2ISP_IF_EB]\t= &dcam2isp_if_eb.common.hw,\n+\t\t[CLK_ISP2DCAM_IF_EB]\t= &isp2dcam_if_eb.common.hw,\n+\t\t[CLK_ISP_LCLK_EB]\t= &isp_lclk_eb.common.hw,\n+\t\t[CLK_ISP_ICLK_EB]\t= &isp_iclk_eb.common.hw,\n+\t\t[CLK_ISP_MCLK_EB]\t= &isp_mclk_eb.common.hw,\n+\t\t[CLK_ISP_PCLK_EB]\t= &isp_pclk_eb.common.hw,\n+\t\t[CLK_ISP_ISP2DCAM_EB]\t= &isp_isp2dcam_eb.common.hw,\n+\t\t[CLK_DCAM0_IF_EB]\t= &dcam0_if_eb.common.hw,\n+\t\t[CLK_CLK26M_IF_EB]\t= &clk26m_if_eb.common.hw,\n+\t\t[CLK_CPHY0_GATE]\t= &cphy0_gate.common.hw,\n+\t\t[CLK_MIPI_CSI0_GATE]\t= &mipi_csi0_gate.common.hw,\n+\t\t[CLK_CPHY1_GATE]\t= &cphy1_gate.common.hw,\n+\t\t[CLK_MIPI_CSI1]\t\t= &mipi_csi1.common.hw,\n+\t\t[CLK_DCAM0_AXI_GATE]\t= &dcam0_axi_gate.common.hw,\n+\t\t[CLK_DCAM1_AXI_GATE]\t= &dcam1_axi_gate.common.hw,\n+\t\t[CLK_SENSOR0_GATE]\t= &sensor0_gate.common.hw,\n+\t\t[CLK_SENSOR1_GATE]\t= &sensor1_gate.common.hw,\n+\t\t[CLK_JPG0_AXI_GATE]\t= &jpg0_axi_gate.common.hw,\n+\t\t[CLK_GPG1_AXI_GATE]\t= &gpg1_axi_gate.common.hw,\n+\t\t[CLK_ISP0_AXI_GATE]\t= &isp0_axi_gate.common.hw,\n+\t\t[CLK_ISP1_AXI_GATE]\t= &isp1_axi_gate.common.hw,\n+\t\t[CLK_ISP2_AXI_GATE]\t= &isp2_axi_gate.common.hw,\n+\t\t[CLK_CPP_AXI_GATE]\t= &cpp_axi_gate.common.hw,\n+\t\t[CLK_D0_IF_AXI_GATE]\t= &d0_if_axi_gate.common.hw,\n+\t\t[CLK_D2I_IF_AXI_GATE]\t= &d2i_if_axi_gate.common.hw,\n+\t\t[CLK_I2D_IF_AXI_GATE]\t= &i2d_if_axi_gate.common.hw,\n+\t\t[CLK_SPARE_AXI_GATE]\t= &spare_axi_gate.common.hw,\n+\t\t[CLK_SENSOR2_GATE]\t= &sensor2_gate.common.hw,\n+\t\t[CLK_D0IF_IN_D_EN]\t= &d0if_in_d_en.common.hw,\n+\t\t[CLK_D1IF_IN_D_EN]\t= &d1if_in_d_en.common.hw,\n+\t\t[CLK_D0IF_IN_D2I_EN]\t= &d0if_in_d2i_en.common.hw,\n+\t\t[CLK_D1IF_IN_D2I_EN]\t= &d1if_in_d2i_en.common.hw,\n+\t\t[CLK_IA_IN_D2I_EN]\t= &ia_in_d2i_en.common.hw,\n+\t\t[CLK_IB_IN_D2I_EN]\t= &ib_in_d2i_en.common.hw,\n+\t\t[CLK_IC_IN_D2I_EN]\t= &ic_in_d2i_en.common.hw,\n+\t\t[CLK_IA_IN_I_EN]\t= &ia_in_i_en.common.hw,\n+\t\t[CLK_IB_IN_I_EN]\t= &ib_in_i_en.common.hw,\n+\t\t[CLK_IC_IN_I_EN]\t= &ic_in_i_en.common.hw,\n+\t},\n+\t.num\t= CLK_CAM_GATE_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_cam_gate_desc = {\n+\t.clk_clks\t= sc9860_cam_gate,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_cam_gate),\n+\t.hw_clks\t= &sc9860_cam_gate_hws,\n+};\n+\n+static SPRD_MUX_CLK(ahb_disp, \"ahb-disp\", ahb_parents, NULL,\t0x20,\n+\t\t    0, 2, SC9860_MUX_FLAG);\n+static SPRD_COMP_CLK(dispc0_dpi, \"dispc0-dpi\", dispc_parents,\t0x34,\n+\t\t     0, 0, 2, 8, 2, 0);\n+static SPRD_COMP_CLK(dispc1_dpi, \"dispc1-dpi\", dispc_parents,\t0x40,\n+\t\t     0, 0, 2, 8, 2, 0);\n+\n+static struct sprd_clk_common *sc9860_disp_clk[] = {\n+\t/* address base is 0x63000000 */\n+\t&ahb_disp.common,\n+\t&dispc0_dpi.common,\n+\t&dispc1_dpi.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_disp_clk_hws = {\n+\t.hws\t= {\n+\t\t[CLK_AHB_DISP]\t\t= &ahb_disp.common.hw,\n+\t\t[CLK_DISPC0_DPI]\t= &dispc0_dpi.common.hw,\n+\t\t[CLK_DISPC1_DPI]\t= &dispc1_dpi.common.hw,\n+\t},\n+\t.num\t= CLK_DISP_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_disp_clk_desc = {\n+\t.clk_clks\t= sc9860_disp_clk,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_disp_clk),\n+\t.hw_clks\t= &sc9860_disp_clk_hws,\n+};\n+\n+static SPRD_GATE_CLK(dispc0_eb,\t\t\"dispc0-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(0), 0, 0);\n+static SPRD_GATE_CLK(dispc1_eb,\t\t\"dispc1-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(1), 0, 0);\n+static SPRD_GATE_CLK(dispc_mmu_eb,\t\"dispc-mmu-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(2), 0, 0);\n+static SPRD_GATE_CLK(gsp0_eb,\t\t\"gsp0-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(3), 0, 0);\n+static SPRD_GATE_CLK(gsp1_eb,\t\t\"gsp1-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(4), 0, 0);\n+static SPRD_GATE_CLK(gsp0_mmu_eb,\t\"gsp0-mmu-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(5), 0, 0);\n+static SPRD_GATE_CLK(gsp1_mmu_eb,\t\"gsp1-mmu-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(6), 0, 0);\n+static SPRD_GATE_CLK(dsi0_eb,\t\t\"dsi0-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(7), 0, 0);\n+static SPRD_GATE_CLK(dsi1_eb,\t\t\"dsi1-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(8), 0, 0);\n+static SPRD_GATE_CLK(disp_ckg_eb,\t\"disp-ckg-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(9), 0, 0);\n+static SPRD_GATE_CLK(disp_gpu_eb,\t\"disp-gpu-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(10), 0, 0);\n+static SPRD_GATE_CLK(gpu_mtx_eb,\t\"gpu-mtx-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(13), 0, 0);\n+static SPRD_GATE_CLK(gsp_mtx_eb,\t\"gsp-mtx-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(14), 0, 0);\n+static SPRD_GATE_CLK(tmc_mtx_eb,\t\"tmc-mtx-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(15), 0, 0);\n+static SPRD_GATE_CLK(dispc_mtx_eb,\t\"dispc-mtx-eb\",\t\"ahb-disp\", 0x0,\n+\t\t     0x1000, BIT(16), 0, 0);\n+static SPRD_GATE_CLK(dphy0_gate,\t\"dphy0-gate\",\t\"ahb-disp\", 0x8,\n+\t\t     0, BIT(0), 0, 0);\n+static SPRD_GATE_CLK(dphy1_gate,\t\"dphy1-gate\",\t\"ahb-disp\", 0x8,\n+\t\t     0, BIT(1), 0, 0);\n+static SPRD_GATE_CLK(gsp0_a_gate,\t\"gsp0-a-gate\",\t\"ahb-disp\", 0x8,\n+\t\t     0, BIT(2), 0, 0);\n+static SPRD_GATE_CLK(gsp1_a_gate,\t\"gsp1-a-gate\",\t\"ahb-disp\", 0x8,\n+\t\t     0, BIT(3), 0, 0);\n+static SPRD_GATE_CLK(gsp0_f_gate,\t\"gsp0-f-gate\",\t\"ahb-disp\", 0x8,\n+\t\t     0, BIT(4), 0, 0);\n+static SPRD_GATE_CLK(gsp1_f_gate,\t\"gsp1-f-gate\",\t\"ahb-disp\", 0x8,\n+\t\t     0, BIT(5), 0, 0);\n+static SPRD_GATE_CLK(d_mtx_f_gate,\t\"d-mtx-f-gate\",\t\"ahb-disp\", 0x8,\n+\t\t     0, BIT(6), 0, 0);\n+static SPRD_GATE_CLK(d_mtx_a_gate,\t\"d-mtx-a-gate\",\t\"ahb-disp\", 0x8,\n+\t\t     0, BIT(7), 0, 0);\n+static SPRD_GATE_CLK(d_noc_f_gate,\t\"d-noc-f-gate\",\t\"ahb-disp\", 0x8,\n+\t\t     0, BIT(8), 0, 0);\n+static SPRD_GATE_CLK(d_noc_a_gate,\t\"d-noc-a-gate\",\t\"ahb-disp\", 0x8,\n+\t\t     0, BIT(9), 0, 0);\n+static SPRD_GATE_CLK(gsp_mtx_f_gate, \"gsp-mtx-f-gate\", \"ahb-disp\",  0x8,\n+\t\t     0, BIT(10), 0, 0);\n+static SPRD_GATE_CLK(gsp_mtx_a_gate, \"gsp-mtx-a-gate\", \"ahb-disp\",  0x8,\n+\t\t     0, BIT(11), 0, 0);\n+static SPRD_GATE_CLK(gsp_noc_f_gate, \"gsp-noc-f-gate\", \"ahb-disp\",  0x8,\n+\t\t     0, BIT(12), 0, 0);\n+static SPRD_GATE_CLK(gsp_noc_a_gate, \"gsp-noc-a-gate\", \"ahb-disp\",  0x8,\n+\t\t     0, BIT(13), 0, 0);\n+static SPRD_GATE_CLK(dispm0idle_gate, \"dispm0idle-gate\", \"ahb-disp\", 0x8,\n+\t\t     0, BIT(14), 0, 0);\n+static SPRD_GATE_CLK(gspm0idle_gate, \"gspm0idle-gate\", \"ahb-disp\",  0x8,\n+\t\t     0, BIT(15), 0, 0);\n+\n+static struct sprd_clk_common *sc9860_disp_gate[] = {\n+\t/* address base is 0x63100000 */\n+\t&dispc0_eb.common,\n+\t&dispc1_eb.common,\n+\t&dispc_mmu_eb.common,\n+\t&gsp0_eb.common,\n+\t&gsp1_eb.common,\n+\t&gsp0_mmu_eb.common,\n+\t&gsp1_mmu_eb.common,\n+\t&dsi0_eb.common,\n+\t&dsi1_eb.common,\n+\t&disp_ckg_eb.common,\n+\t&disp_gpu_eb.common,\n+\t&gpu_mtx_eb.common,\n+\t&gsp_mtx_eb.common,\n+\t&tmc_mtx_eb.common,\n+\t&dispc_mtx_eb.common,\n+\t&dphy0_gate.common,\n+\t&dphy1_gate.common,\n+\t&gsp0_a_gate.common,\n+\t&gsp1_a_gate.common,\n+\t&gsp0_f_gate.common,\n+\t&gsp1_f_gate.common,\n+\t&d_mtx_f_gate.common,\n+\t&d_mtx_a_gate.common,\n+\t&d_noc_f_gate.common,\n+\t&d_noc_a_gate.common,\n+\t&gsp_mtx_f_gate.common,\n+\t&gsp_mtx_a_gate.common,\n+\t&gsp_noc_f_gate.common,\n+\t&gsp_noc_a_gate.common,\n+\t&dispm0idle_gate.common,\n+\t&gspm0idle_gate.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_disp_gate_hws = {\n+\t.hws\t= {\n+\t\t[CLK_DISPC0_EB]\t\t= &dispc0_eb.common.hw,\n+\t\t[CLK_DISPC1_EB]\t\t= &dispc1_eb.common.hw,\n+\t\t[CLK_DISPC_MMU_EB]\t= &dispc_mmu_eb.common.hw,\n+\t\t[CLK_GSP0_EB]\t\t= &gsp0_eb.common.hw,\n+\t\t[CLK_GSP1_EB]\t\t= &gsp1_eb.common.hw,\n+\t\t[CLK_GSP0_MMU_EB]\t= &gsp0_mmu_eb.common.hw,\n+\t\t[CLK_GSP1_MMU_EB]\t= &gsp1_mmu_eb.common.hw,\n+\t\t[CLK_DSI0_EB]\t\t= &dsi0_eb.common.hw,\n+\t\t[CLK_DSI1_EB]\t\t= &dsi1_eb.common.hw,\n+\t\t[CLK_DISP_CKG_EB]\t= &disp_ckg_eb.common.hw,\n+\t\t[CLK_DISP_GPU_EB]\t= &disp_gpu_eb.common.hw,\n+\t\t[CLK_GPU_MTX_EB]\t= &gpu_mtx_eb.common.hw,\n+\t\t[CLK_GSP_MTX_EB]\t= &gsp_mtx_eb.common.hw,\n+\t\t[CLK_TMC_MTX_EB]\t= &tmc_mtx_eb.common.hw,\n+\t\t[CLK_DISPC_MTX_EB]\t= &dispc_mtx_eb.common.hw,\n+\t\t[CLK_DPHY0_GATE]\t= &dphy0_gate.common.hw,\n+\t\t[CLK_DPHY1_GATE]\t= &dphy1_gate.common.hw,\n+\t\t[CLK_GSP0_A_GATE]\t= &gsp0_a_gate.common.hw,\n+\t\t[CLK_GSP1_A_GATE]\t= &gsp1_a_gate.common.hw,\n+\t\t[CLK_GSP0_F_GATE]\t= &gsp0_f_gate.common.hw,\n+\t\t[CLK_GSP1_F_GATE]\t= &gsp1_f_gate.common.hw,\n+\t\t[CLK_D_MTX_F_GATE]\t= &d_mtx_f_gate.common.hw,\n+\t\t[CLK_D_MTX_A_GATE]\t= &d_mtx_a_gate.common.hw,\n+\t\t[CLK_D_NOC_F_GATE]\t= &d_noc_f_gate.common.hw,\n+\t\t[CLK_D_NOC_A_GATE]\t= &d_noc_a_gate.common.hw,\n+\t\t[CLK_GSP_MTX_F_GATE]\t= &gsp_mtx_f_gate.common.hw,\n+\t\t[CLK_GSP_MTX_A_GATE]\t= &gsp_mtx_a_gate.common.hw,\n+\t\t[CLK_GSP_NOC_F_GATE]\t= &gsp_noc_f_gate.common.hw,\n+\t\t[CLK_GSP_NOC_A_GATE]\t= &gsp_noc_a_gate.common.hw,\n+\t\t[CLK_DISPM0IDLE_GATE]\t= &dispm0idle_gate.common.hw,\n+\t\t[CLK_GSPM0IDLE_GATE]\t= &gspm0idle_gate.common.hw,\n+\t},\n+\t.num\t= CLK_DISP_GATE_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_disp_gate_desc = {\n+\t.clk_clks\t= sc9860_disp_gate,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_disp_gate),\n+\t.hw_clks\t= &sc9860_disp_gate_hws,\n+};\n+\n+static SPRD_GATE_CLK(sim0_eb,\t\"sim0-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(0), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(iis0_eb,\t\"iis0-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(1), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(iis1_eb,\t\"iis1-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(2), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(iis2_eb,\t\"iis2-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(3), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(iis3_eb,\t\"iis3-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(4), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(spi0_eb,\t\"spi0-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(5), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(spi1_eb,\t\"spi1-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(6), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(spi2_eb,\t\"spi2-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(7), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(i2c0_eb,\t\"i2c0-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(8), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(i2c1_eb,\t\"i2c1-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(9), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(i2c2_eb,\t\"i2c2-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(10), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(i2c3_eb,\t\"i2c3-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(11), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(i2c4_eb,\t\"i2c4-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(12), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(i2c5_eb,\t\"i2c5-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(13), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(uart0_eb,\t\"uart0-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(14), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(uart1_eb,\t\"uart1-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(15), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(uart2_eb,\t\"uart2-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(16), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(uart3_eb,\t\"uart3-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(17), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(uart4_eb,\t\"uart4-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(18), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(ap_ckg_eb,\t\"ap-ckg-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(19), CLK_IGNORE_UNUSED, 0);\n+static SPRD_GATE_CLK(spi3_eb,\t\"spi3-eb\",\t\"ap-apb\", 0x0,\n+\t\t     0x1000, BIT(20), CLK_IGNORE_UNUSED, 0);\n+\n+static struct sprd_clk_common *sc9860_apapb_gate[] = {\n+\t/* address base is 0x70b00000 */\n+\t&sim0_eb.common,\n+\t&iis0_eb.common,\n+\t&iis1_eb.common,\n+\t&iis2_eb.common,\n+\t&iis3_eb.common,\n+\t&spi0_eb.common,\n+\t&spi1_eb.common,\n+\t&spi2_eb.common,\n+\t&i2c0_eb.common,\n+\t&i2c1_eb.common,\n+\t&i2c2_eb.common,\n+\t&i2c3_eb.common,\n+\t&i2c4_eb.common,\n+\t&i2c5_eb.common,\n+\t&uart0_eb.common,\n+\t&uart1_eb.common,\n+\t&uart2_eb.common,\n+\t&uart3_eb.common,\n+\t&uart4_eb.common,\n+\t&ap_ckg_eb.common,\n+\t&spi3_eb.common,\n+};\n+\n+static struct clk_hw_onecell_data sc9860_apapb_gate_hws = {\n+\t.hws\t= {\n+\t\t[CLK_SIM0_EB]\t\t= &sim0_eb.common.hw,\n+\t\t[CLK_IIS0_EB]\t\t= &iis0_eb.common.hw,\n+\t\t[CLK_IIS1_EB]\t\t= &iis1_eb.common.hw,\n+\t\t[CLK_IIS2_EB]\t\t= &iis2_eb.common.hw,\n+\t\t[CLK_IIS3_EB]\t\t= &iis3_eb.common.hw,\n+\t\t[CLK_SPI0_EB]\t\t= &spi0_eb.common.hw,\n+\t\t[CLK_SPI1_EB]\t\t= &spi1_eb.common.hw,\n+\t\t[CLK_SPI2_EB]\t\t= &spi2_eb.common.hw,\n+\t\t[CLK_I2C0_EB]\t\t= &i2c0_eb.common.hw,\n+\t\t[CLK_I2C1_EB]\t\t= &i2c1_eb.common.hw,\n+\t\t[CLK_I2C2_EB]\t\t= &i2c2_eb.common.hw,\n+\t\t[CLK_I2C3_EB]\t\t= &i2c3_eb.common.hw,\n+\t\t[CLK_I2C4_EB]\t\t= &i2c4_eb.common.hw,\n+\t\t[CLK_I2C5_EB]\t\t= &i2c5_eb.common.hw,\n+\t\t[CLK_UART0_EB]\t\t= &uart0_eb.common.hw,\n+\t\t[CLK_UART1_EB]\t\t= &uart1_eb.common.hw,\n+\t\t[CLK_UART2_EB]\t\t= &uart2_eb.common.hw,\n+\t\t[CLK_UART3_EB]\t\t= &uart3_eb.common.hw,\n+\t\t[CLK_UART4_EB]\t\t= &uart4_eb.common.hw,\n+\t\t[CLK_AP_CKG_EB]\t\t= &ap_ckg_eb.common.hw,\n+\t\t[CLK_SPI3_EB]\t\t= &spi3_eb.common.hw,\n+\t},\n+\t.num\t= CLK_APAPB_GATE_NUM,\n+};\n+\n+static const struct sprd_clk_desc sc9860_apapb_gate_desc = {\n+\t.clk_clks\t= sc9860_apapb_gate,\n+\t.num_clk_clks\t= ARRAY_SIZE(sc9860_apapb_gate),\n+\t.hw_clks\t= &sc9860_apapb_gate_hws,\n+};\n+\n+static const struct of_device_id sprd_sc9860_clk_ids[] = {\n+\t{ .compatible = \"sprd,sc9860-pmu-gate\",\t\t/* 0x402b */\n+\t  .data = &sc9860_pmu_gate_desc },\n+\t{ .compatible = \"sprd,sc9860-pll\",\t\t/* 0x4040 */\n+\t  .data = &sc9860_pll_desc },\n+\t{ .compatible = \"sprd,sc9860-ap-clk\",\t\t/* 0x2000 */\n+\t  .data = &sc9860_ap_clk_desc },\n+\t{ .compatible = \"sprd,sc9860-aon-prediv\",\t/* 0x402d */\n+\t  .data = &sc9860_aon_prediv_desc },\n+\t{ .compatible = \"sprd,sc9860-apahb-gate\",\t/* 0x2021 */\n+\t  .data = &sc9860_apahb_gate_desc },\n+\t{ .compatible = \"sprd,sc9860-aon-gate\",\t\t/* 0x402e */\n+\t  .data = &sc9860_aon_gate_desc },\n+\t{ .compatible = \"sprd,sc9860-aonsecure-clk\",\t/* 0x4088 */\n+\t  .data = &sc9860_aonsecure_clk_desc },\n+\t{ .compatible = \"sprd,sc9860-agcp-gate\",\t/* 0x415e */\n+\t  .data = &sc9860_agcp_gate_desc },\n+\t{ .compatible = \"sprd,sc9860-gpu-clk\",\t\t/* 0x6020 */\n+\t  .data = &sc9860_gpu_clk_desc },\n+\t{ .compatible = \"sprd,sc9860-vsp-clk\",\t\t/* 0x6100 */\n+\t  .data = &sc9860_vsp_clk_desc },\n+\t{ .compatible = \"sprd,sc9860-vsp-gate\",\t\t/* 0x6110 */\n+\t  .data = &sc9860_vsp_gate_desc },\n+\t{ .compatible = \"sprd,sc9860-cam-clk\",\t\t/* 0x6200 */\n+\t  .data = &sc9860_cam_clk_desc },\n+\t{ .compatible = \"sprd,sc9860-cam-gate\",\t\t/* 0x6210 */\n+\t  .data = &sc9860_cam_gate_desc },\n+\t{ .compatible = \"sprd,sc9860-disp-clk\",\t\t/* 0x6300 */\n+\t  .data = &sc9860_disp_clk_desc },\n+\t{ .compatible = \"sprd,sc9860-disp-gate\",\t/* 0x6310 */\n+\t  .data = &sc9860_disp_gate_desc },\n+\t{ .compatible = \"sprd,sc9860-apapb-gate\",\t/* 0x70b0 */\n+\t  .data = &sc9860_apapb_gate_desc },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, sprd_sc9860_clk_ids);\n+\n+static int sc9860_clk_probe(struct platform_device *pdev)\n+{\n+\tint ret = 0;\n+\tconst struct of_device_id *match;\n+\tconst struct sprd_clk_desc *desc;\n+\n+\tmatch = of_match_node(sprd_sc9860_clk_ids, pdev->dev.of_node);\n+\tif (!match) {\n+\t\tpr_err(\"%s: of_match_node() failed.\", __func__);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tdesc = match->data;\n+\tsprd_clk_regmap_init(pdev, desc);\n+\n+\tret = sprd_clk_probe(pdev->dev.of_node, desc->hw_clks);\n+\tif (ret == 0)\n+\t\tpr_info(\"%s: %u clocks have been registered now.\\n\",\n+\t\tmatch->compatible, desc->hw_clks->num);\n+\n+\treturn ret;\n+}\n+\n+static struct platform_driver sc9860_clk_driver = {\n+\t.probe\t= sc9860_clk_probe,\n+\t.driver\t= {\n+\t\t.name\t= \"sc9860-clk\",\n+\t\t.of_match_table\t= sprd_sc9860_clk_ids,\n+\t},\n+};\n+module_platform_driver(sc9860_clk_driver);\n+\n+MODULE_DESCRIPTION(\"Spreadtrum SC9860 Clock Driver\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_ALIAS(\"platform:sc9860-clk\");\ndiff --git a/include/dt-bindings/clock/sprd,sc9860-clk.h b/include/dt-bindings/clock/sprd,sc9860-clk.h\nnew file mode 100644\nindex 0000000..48e6052\n--- /dev/null\n+++ b/include/dt-bindings/clock/sprd,sc9860-clk.h\n@@ -0,0 +1,408 @@\n+/*\n+ * Spreadtrum SC9860 platform clocks\n+ *\n+ * Copyright (C) 2017, Spreadtrum Communications Inc.\n+ *\n+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_SC9860_H_\n+#define _DT_BINDINGS_CLK_SC9860_H_\n+\n+#define\tCLK_EXT_RCO_100M\t0\n+#define\tCLK_EXT_32K\t\t1\n+#define\tCLK_FAC_4M\t\t2\n+#define\tCLK_FAC_2M\t\t3\n+#define\tCLK_FAC_1M\t\t4\n+#define\tCLK_FAC_250K\t\t5\n+#define\tCLK_FAC_RPLL0_26M\t6\n+#define\tCLK_FAC_RPLL1_26M\t7\n+#define\tCLK_FAC_RCO25M\t\t8\n+#define\tCLK_FAC_RCO4M\t\t9\n+#define\tCLK_FAC_RCO2M\t\t10\n+#define\tCLK_FAC_3K2\t\t11\n+#define\tCLK_FAC_1K\t\t12\n+#define\tCLK_MPLL0_GATE\t\t13\n+#define\tCLK_MPLL1_GATE\t\t14\n+#define\tCLK_DPLL0_GATE\t\t15\n+#define\tCLK_DPLL1_GATE\t\t16\n+#define\tCLK_LTEPLL0_GATE\t17\n+#define\tCLK_TWPLL_GATE\t\t18\n+#define\tCLK_LTEPLL1_GATE\t19\n+#define\tCLK_RPLL0_GATE\t\t20\n+#define\tCLK_RPLL1_GATE\t\t21\n+#define\tCLK_CPPLL_GATE\t\t22\n+#define\tCLK_GPLL_GATE\t\t23\n+#define CLK_PMU_GATE_NUM\t(CLK_GPLL_GATE + 1)\n+\n+#define\tCLK_MPLL0\t\t0\n+#define\tCLK_MPLL1\t\t1\n+#define\tCLK_DPLL0\t\t2\n+#define\tCLK_DPLL1\t\t3\n+#define\tCLK_RPLL0\t\t4\n+#define\tCLK_RPLL1\t\t5\n+#define\tCLK_TWPLL\t\t6\n+#define\tCLK_LTEPLL0\t\t7\n+#define\tCLK_LTEPLL1\t\t8\n+#define\tCLK_GPLL\t\t9\n+#define\tCLK_CPPLL\t\t10\n+#define\tCLK_GPLL_42M5\t\t11\n+#define\tCLK_TWPLL_768M\t\t12\n+#define\tCLK_TWPLL_384M\t\t13\n+#define\tCLK_TWPLL_192M\t\t14\n+#define\tCLK_TWPLL_96M\t\t15\n+#define\tCLK_TWPLL_48M\t\t16\n+#define\tCLK_TWPLL_24M\t\t17\n+#define\tCLK_TWPLL_12M\t\t18\n+#define\tCLK_TWPLL_512M\t\t19\n+#define\tCLK_TWPLL_256M\t\t20\n+#define\tCLK_TWPLL_128M\t\t21\n+#define\tCLK_TWPLL_64M\t\t22\n+#define\tCLK_TWPLL_307M2\t\t23\n+#define\tCLK_TWPLL_153M6\t\t24\n+#define\tCLK_TWPLL_76M8\t\t25\n+#define\tCLK_TWPLL_51M2\t\t26\n+#define\tCLK_TWPLL_38M4\t\t27\n+#define\tCLK_TWPLL_19M2\t\t28\n+#define\tCLK_L0_614M4\t\t29\n+#define\tCLK_L0_409M6\t\t30\n+#define\tCLK_L0_38M\t\t31\n+#define\tCLK_L1_38M\t\t32\n+#define\tCLK_RPLL0_192M\t\t33\n+#define\tCLK_RPLL0_96M\t\t34\n+#define\tCLK_RPLL0_48M\t\t35\n+#define\tCLK_RPLL1_468M\t\t36\n+#define\tCLK_RPLL1_192M\t\t37\n+#define\tCLK_RPLL1_96M\t\t38\n+#define\tCLK_RPLL1_64M\t\t39\n+#define\tCLK_RPLL1_48M\t\t40\n+#define\tCLK_DPLL0_50M\t\t41\n+#define\tCLK_DPLL1_50M\t\t42\n+#define\tCLK_CPPLL_50M\t\t43\n+#define\tCLK_M0_39M\t\t44\n+#define\tCLK_M1_63M\t\t45\n+#define CLK_PLL_NUM\t\t(CLK_M1_63M + 1)\n+\n+\n+#define\tCLK_AP_APB\t\t0\n+#define\tCLK_AP_USB3\t\t1\n+#define\tCLK_UART0\t\t2\n+#define\tCLK_UART1\t\t3\n+#define\tCLK_UART2\t\t4\n+#define\tCLK_UART3\t\t5\n+#define\tCLK_UART4\t\t6\n+#define\tCLK_I2C0\t\t7\n+#define\tCLK_I2C1\t\t8\n+#define\tCLK_I2C2\t\t9\n+#define\tCLK_I2C3\t\t10\n+#define\tCLK_I2C4\t\t11\n+#define\tCLK_I2C5\t\t12\n+#define\tCLK_SPI0\t\t13\n+#define\tCLK_SPI1\t\t14\n+#define\tCLK_SPI2\t\t15\n+#define\tCLK_SPI3\t\t16\n+#define\tCLK_IIS0\t\t17\n+#define\tCLK_IIS1\t\t18\n+#define\tCLK_IIS2\t\t19\n+#define\tCLK_IIS3\t\t20\n+#define CLK_AP_CLK_NUM\t\t(CLK_IIS3 + 1)\n+\n+#define\tCLK_AON_APB\t\t0\n+#define\tCLK_AUX0\t\t1\n+#define\tCLK_AUX1\t\t2\n+#define\tCLK_AUX2\t\t3\n+#define\tCLK_PROBE\t\t4\n+#define\tCLK_SP_AHB\t\t5\n+#define\tCLK_CCI\t\t\t6\n+#define\tCLK_GIC\t\t\t7\n+#define\tCLK_CSSYS\t\t8\n+#define\tCLK_SDIO0_2X\t\t9\n+#define\tCLK_SDIO1_2X\t\t10\n+#define\tCLK_SDIO2_2X\t\t11\n+#define\tCLK_EMMC_2X\t\t12\n+#define\tCLK_SDIO0_1X\t\t13\n+#define\tCLK_SDIO1_1X\t\t14\n+#define\tCLK_SDIO2_1X\t\t15\n+#define\tCLK_EMMC_1X\t\t16\n+#define\tCLK_ADI\t\t\t17\n+#define\tCLK_PWM0\t\t18\n+#define\tCLK_PWM1\t\t19\n+#define\tCLK_PWM2\t\t20\n+#define\tCLK_PWM3\t\t21\n+#define\tCLK_EFUSE\t\t22\n+#define\tCLK_CM3_UART0\t\t23\n+#define\tCLK_CM3_UART1\t\t24\n+#define\tCLK_THM\t\t\t25\n+#define\tCLK_CM3_I2C0\t\t26\n+#define\tCLK_CM3_I2C1\t\t27\n+#define\tCLK_CM4_SPI\t\t28\n+#define\tCLK_AON_I2C\t\t29\n+#define\tCLK_AVS\t\t\t30\n+#define\tCLK_CA53_DAP\t\t31\n+#define\tCLK_CA53_TS\t\t32\n+#define\tCLK_DJTAG_TCK\t\t33\n+#define\tCLK_PMU\t\t\t34\n+#define\tCLK_PMU_26M\t\t35\n+#define\tCLK_DEBOUNCE\t\t36\n+#define\tCLK_OTG2_REF\t\t37\n+#define\tCLK_USB3_REF\t\t38\n+#define\tCLK_AP_AXI\t\t39\n+#define CLK_AON_PREDIV_NUM\t(CLK_AP_AXI + 1)\n+\n+#define\tCLK_USB3_EB\t\t0\n+#define\tCLK_USB3_SUSPEND_EB\t1\n+#define\tCLK_USB3_REF_EB\t\t2\n+#define\tCLK_DMA_EB\t\t3\n+#define\tCLK_SDIO0_EB\t\t4\n+#define\tCLK_SDIO1_EB\t\t5\n+#define\tCLK_SDIO2_EB\t\t6\n+#define\tCLK_EMMC_EB\t\t7\n+#define\tCLK_ROM_EB\t\t8\n+#define\tCLK_BUSMON_EB\t\t9\n+#define\tCLK_CC63S_EB\t\t10\n+#define\tCLK_CC63P_EB\t\t11\n+#define\tCLK_CE0_EB\t\t12\n+#define\tCLK_CE1_EB\t\t13\n+#define CLK_APAHB_GATE_NUM\t(CLK_CE1_EB + 1)\n+\n+#define\tCLK_AVS_LIT_EB\t\t0\n+#define\tCLK_AVS_BIG_EB\t\t1\n+#define\tCLK_AP_INTC5_EB\t\t2\n+#define\tCLK_GPIO_EB\t\t3\n+#define\tCLK_PWM0_EB\t\t4\n+#define\tCLK_PWM1_EB\t\t5\n+#define\tCLK_PWM2_EB\t\t6\n+#define\tCLK_PWM3_EB\t\t7\n+#define\tCLK_KPD_EB\t\t8\n+#define\tCLK_AON_SYS_EB\t\t9\n+#define\tCLK_AP_SYS_EB\t\t10\n+#define\tCLK_AON_TMR_EB\t\t11\n+#define\tCLK_AP_TMR0_EB\t\t12\n+#define\tCLK_EFUSE_EB\t\t13\n+#define\tCLK_EIC_EB\t\t14\n+#define\tCLK_PUB1_REG_EB\t\t15\n+#define\tCLK_ADI_EB\t\t16\n+#define\tCLK_AP_INTC0_EB\t\t17\n+#define\tCLK_AP_INTC1_EB\t\t18\n+#define\tCLK_AP_INTC2_EB\t\t19\n+#define\tCLK_AP_INTC3_EB\t\t20\n+#define\tCLK_AP_INTC4_EB\t\t21\n+#define\tCLK_SPLK_EB\t\t22\n+#define\tCLK_MSPI_EB\t\t23\n+#define\tCLK_PUB0_REG_EB\t\t24\n+#define\tCLK_PIN_EB\t\t25\n+#define\tCLK_AON_CKG_EB\t\t26\n+#define\tCLK_GPU_EB\t\t27\n+#define\tCLK_APCPU_TS0_EB\t28\n+#define\tCLK_APCPU_TS1_EB\t29\n+#define\tCLK_DAP_EB\t\t30\n+#define\tCLK_I2C_EB\t\t31\n+#define\tCLK_PMU_EB\t\t32\n+#define\tCLK_THM_EB\t\t33\n+#define\tCLK_AUX0_EB\t\t34\n+#define\tCLK_AUX1_EB\t\t35\n+#define\tCLK_AUX2_EB\t\t36\n+#define\tCLK_PROBE_EB\t\t37\n+#define\tCLK_GPU0_AVS_EB\t\t38\n+#define\tCLK_GPU1_AVS_EB\t\t39\n+#define\tCLK_APCPU_WDG_EB\t40\n+#define\tCLK_AP_TMR1_EB\t\t41\n+#define\tCLK_AP_TMR2_EB\t\t42\n+#define\tCLK_DISP_EMC_EB\t\t43\n+#define\tCLK_ZIP_EMC_EB\t\t44\n+#define\tCLK_GSP_EMC_EB\t\t45\n+#define\tCLK_OSC_AON_EB\t\t46\n+#define\tCLK_LVDS_TRX_EB\t\t47\n+#define\tCLK_LVDS_TCXO_EB\t48\n+#define\tCLK_MDAR_EB\t\t49\n+#define\tCLK_RTC4M0_CAL_EB\t50\n+#define\tCLK_RCT100M_CAL_EB\t51\n+#define\tCLK_DJTAG_EB\t\t52\n+#define\tCLK_MBOX_EB\t\t53\n+#define\tCLK_AON_DMA_EB\t\t54\n+#define\tCLK_DBG_EMC_EB\t\t55\n+#define\tCLK_LVDS_PLL_DIV_EN\t56\n+#define\tCLK_DEF_EB\t\t57\n+#define\tCLK_AON_APB_RSV0\t58\n+#define\tCLK_ORP_JTAG_EB\t\t59\n+#define\tCLK_VSP_EB\t\t60\n+#define\tCLK_CAM_EB\t\t61\n+#define\tCLK_DISP_EB\t\t62\n+#define\tCLK_DBG_AXI_IF_EB\t63\n+#define\tCLK_SDIO0_2X_EN\t\t64\n+#define\tCLK_SDIO1_2X_EN\t\t65\n+#define\tCLK_SDIO2_2X_EN\t\t66\n+#define\tCLK_EMMC_2X_EN\t\t67\n+#define CLK_AON_GATE_NUM\t(CLK_EMMC_2X_EN + 1)\n+\n+#define\tCLK_LIT_MCU\t\t0\n+#define\tCLK_BIG_MCU\t\t1\n+#define CLK_AONSECURE_NUM\t(CLK_BIG_MCU + 1)\n+\n+#define\tCLK_AGCP_IIS0_EB\t0\n+#define\tCLK_AGCP_IIS1_EB\t1\n+#define\tCLK_AGCP_IIS2_EB\t2\n+#define\tCLK_AGCP_IIS3_EB\t3\n+#define\tCLK_AGCP_UART_EB\t4\n+#define\tCLK_AGCP_DMACP_EB\t5\n+#define\tCLK_AGCP_DMAAP_EB\t6\n+#define\tCLK_AGCP_ARC48K_EB\t7\n+#define\tCLK_AGCP_SRC44P1K_EB\t8\n+#define\tCLK_AGCP_MCDT_EB\t9\n+#define\tCLK_AGCP_VBCIFD_EB\t10\n+#define\tCLK_AGCP_VBC_EB\t\t11\n+#define\tCLK_AGCP_SPINLOCK_EB\t12\n+#define\tCLK_AGCP_ICU_EB\t\t13\n+#define\tCLK_AGCP_AP_ASHB_EB\t14\n+#define\tCLK_AGCP_CP_ASHB_EB\t15\n+#define\tCLK_AGCP_AUD_EB\t\t16\n+#define\tCLK_AGCP_AUDIF_EB\t17\n+#define CLK_AGCP_GATE_NUM\t(CLK_AGCP_AUDIF_EB + 1)\n+\n+#define\tCLK_GPU\t\t\t0\n+#define CLK_GPU_NUM\t\t(CLK_GPU + 1)\n+\n+#define\tCLK_AHB_VSP\t\t0\n+#define\tCLK_VSP\t\t\t1\n+#define\tCLK_VSP_ENC\t\t2\n+#define\tCLK_VPP\t\t\t3\n+#define\tCLK_VSP_26M\t\t4\n+#define CLK_VSP_NUM\t\t(CLK_VSP_26M + 1)\n+\n+#define\tCLK_VSP_DEC_EB\t\t0\n+#define\tCLK_VSP_CKG_EB\t\t1\n+#define\tCLK_VSP_MMU_EB\t\t2\n+#define\tCLK_VSP_ENC_EB\t\t3\n+#define\tCLK_VPP_EB\t\t4\n+#define\tCLK_VSP_26M_EB\t\t5\n+#define\tCLK_VSP_AXI_GATE\t6\n+#define\tCLK_VSP_ENC_GATE\t7\n+#define\tCLK_VPP_AXI_GATE\t8\n+#define\tCLK_VSP_BM_GATE\t\t9\n+#define\tCLK_VSP_ENC_BM_GATE\t10\n+#define\tCLK_VPP_BM_GATE\t\t11\n+#define CLK_VSP_GATE_NUM\t(CLK_VPP_BM_GATE + 1)\n+\n+#define\tCLK_AHB_CAM\t\t0\n+#define\tCLK_SENSOR0\t\t1\n+#define\tCLK_SENSOR1\t\t2\n+#define\tCLK_SENSOR2\t\t3\n+#define\tCLK_MIPI_CSI0_EB\t4\n+#define\tCLK_MIPI_CSI1_EB\t5\n+#define CLK_CAM_NUM\t\t(CLK_MIPI_CSI1_EB + 1)\n+\n+#define\tCLK_DCAM0_EB\t\t0\n+#define\tCLK_DCAM1_EB\t\t1\n+#define\tCLK_ISP0_EB\t\t2\n+#define\tCLK_CSI0_EB\t\t3\n+#define\tCLK_CSI1_EB\t\t4\n+#define\tCLK_JPG0_EB\t\t5\n+#define\tCLK_JPG1_EB\t\t6\n+#define\tCLK_CAM_CKG_EB\t\t7\n+#define\tCLK_CAM_MMU_EB\t\t8\n+#define\tCLK_ISP1_EB\t\t9\n+#define\tCLK_CPP_EB\t\t10\n+#define\tCLK_MMU_PF_EB\t\t11\n+#define\tCLK_ISP2_EB\t\t12\n+#define\tCLK_DCAM2ISP_IF_EB\t13\n+#define\tCLK_ISP2DCAM_IF_EB\t14\n+#define\tCLK_ISP_LCLK_EB\t\t15\n+#define\tCLK_ISP_ICLK_EB\t\t16\n+#define\tCLK_ISP_MCLK_EB\t\t17\n+#define\tCLK_ISP_PCLK_EB\t\t18\n+#define\tCLK_ISP_ISP2DCAM_EB\t19\n+#define\tCLK_DCAM0_IF_EB\t\t20\n+#define\tCLK_CLK26M_IF_EB\t21\n+#define\tCLK_CPHY0_GATE\t\t22\n+#define\tCLK_MIPI_CSI0_GATE\t23\n+#define\tCLK_CPHY1_GATE\t\t24\n+#define\tCLK_MIPI_CSI1\t\t25\n+#define\tCLK_DCAM0_AXI_GATE\t26\n+#define\tCLK_DCAM1_AXI_GATE\t27\n+#define\tCLK_SENSOR0_GATE\t28\n+#define\tCLK_SENSOR1_GATE\t29\n+#define\tCLK_JPG0_AXI_GATE\t30\n+#define\tCLK_GPG1_AXI_GATE\t31\n+#define\tCLK_ISP0_AXI_GATE\t32\n+#define\tCLK_ISP1_AXI_GATE\t33\n+#define\tCLK_ISP2_AXI_GATE\t34\n+#define\tCLK_CPP_AXI_GATE\t35\n+#define\tCLK_D0_IF_AXI_GATE\t36\n+#define\tCLK_D2I_IF_AXI_GATE\t37\n+#define\tCLK_I2D_IF_AXI_GATE\t38\n+#define\tCLK_SPARE_AXI_GATE\t39\n+#define\tCLK_SENSOR2_GATE\t40\n+#define\tCLK_D0IF_IN_D_EN\t41\n+#define\tCLK_D1IF_IN_D_EN\t42\n+#define\tCLK_D0IF_IN_D2I_EN\t43\n+#define\tCLK_D1IF_IN_D2I_EN\t44\n+#define\tCLK_IA_IN_D2I_EN\t45\n+#define\tCLK_IB_IN_D2I_EN\t46\n+#define\tCLK_IC_IN_D2I_EN\t47\n+#define\tCLK_IA_IN_I_EN\t\t48\n+#define\tCLK_IB_IN_I_EN\t\t49\n+#define\tCLK_IC_IN_I_EN\t\t50\n+#define CLK_CAM_GATE_NUM\t(CLK_IC_IN_I_EN + 1)\n+\n+#define\tCLK_AHB_DISP\t\t0\n+#define\tCLK_DISPC0_DPI\t\t1\n+#define\tCLK_DISPC1_DPI\t\t2\n+#define CLK_DISP_NUM\t\t(CLK_DISPC1_DPI + 1)\n+\n+#define\tCLK_DISPC0_EB\t\t0\n+#define\tCLK_DISPC1_EB\t\t1\n+#define\tCLK_DISPC_MMU_EB\t2\n+#define\tCLK_GSP0_EB\t\t3\n+#define\tCLK_GSP1_EB\t\t4\n+#define\tCLK_GSP0_MMU_EB\t\t5\n+#define\tCLK_GSP1_MMU_EB\t\t6\n+#define\tCLK_DSI0_EB\t\t7\n+#define\tCLK_DSI1_EB\t\t8\n+#define\tCLK_DISP_CKG_EB\t\t9\n+#define\tCLK_DISP_GPU_EB\t\t10\n+#define\tCLK_GPU_MTX_EB\t\t11\n+#define\tCLK_GSP_MTX_EB\t\t12\n+#define\tCLK_TMC_MTX_EB\t\t13\n+#define\tCLK_DISPC_MTX_EB\t14\n+#define\tCLK_DPHY0_GATE\t\t15\n+#define\tCLK_DPHY1_GATE\t\t16\n+#define\tCLK_GSP0_A_GATE\t\t17\n+#define\tCLK_GSP1_A_GATE\t\t18\n+#define\tCLK_GSP0_F_GATE\t\t19\n+#define\tCLK_GSP1_F_GATE\t\t20\n+#define\tCLK_D_MTX_F_GATE\t21\n+#define\tCLK_D_MTX_A_GATE\t22\n+#define\tCLK_D_NOC_F_GATE\t23\n+#define\tCLK_D_NOC_A_GATE\t24\n+#define\tCLK_GSP_MTX_F_GATE\t25\n+#define\tCLK_GSP_MTX_A_GATE\t26\n+#define\tCLK_GSP_NOC_F_GATE\t27\n+#define\tCLK_GSP_NOC_A_GATE\t28\n+#define\tCLK_DISPM0IDLE_GATE\t29\n+#define\tCLK_GSPM0IDLE_GATE\t30\n+#define CLK_DISP_GATE_NUM\t(CLK_GSPM0IDLE_GATE + 1)\n+\n+#define\tCLK_SIM0_EB\t\t0\n+#define\tCLK_IIS0_EB\t\t1\n+#define\tCLK_IIS1_EB\t\t2\n+#define\tCLK_IIS2_EB\t\t3\n+#define\tCLK_IIS3_EB\t\t4\n+#define\tCLK_SPI0_EB\t\t5\n+#define\tCLK_SPI1_EB\t\t6\n+#define\tCLK_SPI2_EB\t\t7\n+#define\tCLK_I2C0_EB\t\t8\n+#define\tCLK_I2C1_EB\t\t9\n+#define\tCLK_I2C2_EB\t\t10\n+#define\tCLK_I2C3_EB\t\t11\n+#define\tCLK_I2C4_EB\t\t12\n+#define\tCLK_I2C5_EB\t\t13\n+#define\tCLK_UART0_EB\t\t14\n+#define\tCLK_UART1_EB\t\t15\n+#define\tCLK_UART2_EB\t\t16\n+#define\tCLK_UART3_EB\t\t17\n+#define\tCLK_UART4_EB\t\t18\n+#define\tCLK_AP_CKG_EB\t\t19\n+#define\tCLK_SPI3_EB\t\t20\n+#define CLK_APAPB_GATE_NUM\t(CLK_SPI3_EB + 1)\n+\n+#endif /* _DT_BINDINGS_CLK_SC9860_H_ */\n",
    "prefixes": [
        "V3",
        "09/11"
    ]
}