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{
    "id": 833238,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/833238/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20171102065626.21835-3-chunyan.zhang@spreadtrum.com/",
    "project": {
        "id": 37,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/37/?format=api",
        "name": "Devicetree Bindings",
        "link_name": "devicetree-bindings",
        "list_id": "devicetree.vger.kernel.org",
        "list_email": "devicetree@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20171102065626.21835-3-chunyan.zhang@spreadtrum.com>",
    "list_archive_url": null,
    "date": "2017-11-02T06:56:17",
    "name": "[V3,02/11] dt-bindings: Add Spreadtrum clock binding documentation",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "63b4bb2612d7afb73750504d3dc8895dc1ad8168",
    "submitter": {
        "id": 64991,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/64991/?format=api",
        "name": "Chunyan Zhang",
        "email": "chunyan.zhang@spreadtrum.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20171102065626.21835-3-chunyan.zhang@spreadtrum.com/mbox/",
    "series": [
        {
            "id": 11448,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/11448/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=11448",
            "date": "2017-11-02T06:56:15",
            "name": "add clock driver for Spreadtrum platforms",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/11448/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/833238/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/833238/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<devicetree-owner@vger.kernel.org>",
        "X-Original-To": "incoming-dt@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3ySGQ65qyWz9s7c\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu,  2 Nov 2017 18:08:14 +1100 (AEDT)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932705AbdKBHIN (ORCPT <rfc822; incoming-dt@patchwork.ozlabs.org>);\n\tThu, 2 Nov 2017 03:08:13 -0400",
            "from sci-ig2.spreadtrum.com ([222.66.158.135]:61261 \"EHLO\n\tSHSQR01.spreadtrum.com\" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org\n\twith ESMTP id S932607AbdKBHIM (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Thu, 2 Nov 2017 03:08:12 -0400",
            "from ig2.spreadtrum.com (shmbx04.spreadtrum.com [10.0.1.214])\n\tby SHSQR01.spreadtrum.com with ESMTP id vA272Obt015578\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO);\n\tThu, 2 Nov 2017 15:02:24 +0800 (CST)\n\t(envelope-from Chunyan.Zhang@spreadtrum.com)",
            "from SHCAS02.spreadtrum.com (10.0.1.202) by SHMBX04.spreadtrum.com\n\t(10.0.1.214) with Microsoft SMTP Server (TLS) id 15.0.847.32;\n\tThu, 2 Nov 2017 15:02:11 +0800",
            "from localhost (10.0.73.143) by SHCAS02.spreadtrum.com (10.0.1.250)\n\twith Microsoft SMTP Server (TLS) id 15.0.847.32 via Frontend\n\tTransport; Thu, 2 Nov 2017 15:02:11 +0800"
        ],
        "From": "Chunyan Zhang <chunyan.zhang@spreadtrum.com>",
        "To": "Stephen Boyd <sboyd@codeaurora.org>,\n\tMichael Turquette <mturquette@baylibre.com>,\n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>",
        "CC": "Catalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will.deacon@arm.com>, <linux-clk@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, Arnd Bergmann <arnd@arndb.de>,\n\tMark Brown <broonie@kernel.org>,\n\tXiaolong Zhang <xiaolong.zhang@spreadtrum.com>,\n\tBen Li <ben.li@spreadtrum.com>, <linux-arm-kernel@lists.infradead.org>,\n\t<linux-kernel@vger.kernel.org>, Orson Zhai <orson.zhai@spreadtrum.com>,\n\tChunyan Zhang <zhang.lyra@gmail.com>",
        "Subject": "[PATCH V3 02/11] dt-bindings: Add Spreadtrum clock binding\n\tdocumentation",
        "Date": "Thu, 2 Nov 2017 14:56:17 +0800",
        "Message-ID": "<20171102065626.21835-3-chunyan.zhang@spreadtrum.com>",
        "X-Mailer": "git-send-email 2.12.2",
        "In-Reply-To": "<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>",
        "References": "<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-MAIL": "SHSQR01.spreadtrum.com vA272Obt015578",
        "Sender": "devicetree-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<devicetree.vger.kernel.org>",
        "X-Mailing-List": "devicetree@vger.kernel.org"
    },
    "content": "Introduce a new binding with its documentation for Spreadtrum clock\nsub-framework.\n\nSigned-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>\n---\n Documentation/devicetree/bindings/clock/sprd.txt | 55 ++++++++++++++++++++++++\n 1 file changed, 55 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/clock/sprd.txt",
    "diff": "diff --git a/Documentation/devicetree/bindings/clock/sprd.txt b/Documentation/devicetree/bindings/clock/sprd.txt\nnew file mode 100644\nindex 0000000..5c09529\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/clock/sprd.txt\n@@ -0,0 +1,55 @@\n+Spreadtrum Clock Binding\n+------------------------\n+\n+Required properties:\n+- compatible: should contain the following compatible strings:\n+\t- \"sprd,sc9860-pmu-gate\"\n+\t- \"sprd,sc9860-pll\"\n+\t- \"sprd,sc9860-ap-clk\"\n+\t- \"sprd,sc9860-aon-prediv\"\n+\t- \"sprd,sc9860-apahb-gate\"\n+\t- \"sprd,sc9860-aon-gate\"\n+\t- \"sprd,sc9860-aonsecure-clk\"\n+\t- \"sprd,sc9860-agcp-gate\"\n+\t- \"sprd,sc9860-gpu-clk\"\n+\t- \"sprd,sc9860-vsp-clk\"\n+\t- \"sprd,sc9860-vsp-gate\"\n+\t- \"sprd,sc9860-cam-clk\"\n+\t- \"sprd,sc9860-cam-gate\"\n+\t- \"sprd,sc9860-disp-clk\"\n+\t- \"sprd,sc9860-disp-gate\"\n+\t- \"sprd,sc9860-apapb-gate\"\n+\n+- #clock-cells: must be 1\n+\n+- clocks : shall be the input parent clock(s) phandle for the clock.\n+\n+Optional properties:\n+\n+- reg:\tContain the registers base address and length. It must be configured only if no 'sprd,syscon' under the node.\n+\n+- sprd,syscon: phandle to the syscon which is in the same address area with the clock.\n+\n+Example:\n+\n+\tpmu_gate: pmu-gate {\n+\t\tcompatible = \"sprd,sc9860-pmu-gate\";\n+\t\tsprd,syscon = <&pmu_apb>;\n+\t\tclocks = <&ext_26m>;\n+\t\t#clock-cells = <1>;\n+\t};\n+\n+\tpll: pll {\n+\t\tcompatible = \"sprd,sc9860-pll\";\n+\t\tsprd,syscon = <&ana_apb>;\n+\t\tclocks = <&pmu_gate 0>;\n+\t\t#clock-cells = <1>;\n+\t};\n+\n+\tap_clk: clock-controller@20000000 {\n+\t\tcompatible = \"sprd,sc9860-ap-clk\";\n+\t\treg = <0 0x20000000 0 0x400>;\n+\t\tclocks = <&ext_26m>, <&pll 0>,\n+\t\t\t <&pmu_gate 0>;\n+\t\t#clock-cells = <1>;\n+\t};\n",
    "prefixes": [
        "V3",
        "02/11"
    ]
}