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GET /api/1.2/patches/833148/?format=api
{ "id": 833148, "url": "http://patchwork.ozlabs.org/api/1.2/patches/833148/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/20171102003606.19913-6-david.daney@cavium.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/1.2/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20171102003606.19913-6-david.daney@cavium.com>", "list_archive_url": null, "date": "2017-11-02T00:36:04", "name": "[5/7] MIPS: Octeon: Automatically provision CVMSEG space.", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "88c317d2a5b3ba09dcb00a37edfd8e4db82a67eb", "submitter": { "id": 8400, "url": "http://patchwork.ozlabs.org/api/1.2/people/8400/?format=api", "name": "David Daney", "email": "david.daney@cavium.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/1.2/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/20171102003606.19913-6-david.daney@cavium.com/mbox/", "series": [ { "id": 11414, "url": "http://patchwork.ozlabs.org/api/1.2/series/11414/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=11414", "date": "2017-11-02T00:35:59", "name": "Cavium OCTEON-III network driver.", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/11414/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/833148/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/833148/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"YkfgUdwE\"; \n\tdkim-atps=neutral", "spf=none (sender IP is )\n\tsmtp.mailfrom=David.Daney@cavium.com; " ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yS5lc18Klz9t2l\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 2 Nov 2017 11:37:48 +1100 (AEDT)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S934065AbdKBAgt (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tWed, 1 Nov 2017 20:36:49 -0400", "from mail-sn1nam02on0046.outbound.protection.outlook.com\n\t([104.47.36.46]:43314\n\t\"EHLO NAM02-SN1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S934037AbdKBAgq (ORCPT <rfc822;netdev@vger.kernel.org>);\n\tWed, 1 Nov 2017 20:36:46 -0400", "from ddl.caveonetworks.com (50.233.148.156) by\n\tCY4PR07MB3496.namprd07.prod.outlook.com (10.171.252.153) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.178.6; Thu, 2 Nov 2017 00:36:42 +0000" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=64hUgxWJO3gISBjk7i4oHGumBGNP5aRyGeiOcLNk4zk=;\n\tb=YkfgUdwEoetIrmAXidePbXNfdwwEt2VmEOir0Kxwa7QRMsiyBsy7SYInzfW9POTFaPgfY5X975qLyeWqt5H2yvfAFpteu+DfwCrFGjFXdA5joQFMR131QavLeg6rjXDntBIyqDCwqBjXFUXxpOGggdMDc4DDNf+91LWh9DtNLYU=", "From": "David Daney <david.daney@cavium.com>", "To": "linux-mips@linux-mips.org, ralf@linux-mips.org,\n\tJames Hogan <james.hogan@mips.com>, netdev@vger.kernel.org,\n\t\"David S. Miller\" <davem@davemloft.net>,\n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>", "Cc": "linux-kernel@vger.kernel.org, \"Steven J. Hill\" <steven.hill@cavium.com>,\n\tdevicetree@vger.kernel.org, David Daney <david.daney@cavium.com>,\n\tCarlos Munoz <cmunoz@caviumnetworks.com>", "Subject": "[PATCH 5/7] MIPS: Octeon: Automatically provision CVMSEG space.", "Date": "Wed, 1 Nov 2017 17:36:04 -0700", "Message-Id": "<20171102003606.19913-6-david.daney@cavium.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20171102003606.19913-1-david.daney@cavium.com>", "References": "<20171102003606.19913-1-david.daney@cavium.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[50.233.148.156]", "X-ClientProxiedBy": "CO2PR07CA0072.namprd07.prod.outlook.com (10.174.192.40) To\n\tCY4PR07MB3496.namprd07.prod.outlook.com (10.171.252.153)", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "c5081ad2-6914-423b-10f0-08d52189cab5", "X-Microsoft-Antispam": "UriScan:; BCL:0; PCL:0;\n\tRULEID:(22001)(4534020)(4602075)(2017052603199);\n\tSRVR:CY4PR07MB3496; ", "X-Microsoft-Exchange-Diagnostics": [ "1; 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SFP:1101; SCL:1; SRVR:CY4PR07MB3496;\n\tH:ddl.caveonetworks.com; FPR:; SPF:None; PTR:InfoNoRecords;\n\tMX:1; A:1; LANG:en; ", "Received-SPF": "None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "cavium.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 Nov 2017 00:36:42.9299\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "c5081ad2-6914-423b-10f0-08d52189cab5", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "711e4ccf-2e9b-4bcf-a551-4094005b6194", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR07MB3496", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "Remove CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE and automatically calculate\nthe amount of CVMSEG space needed.\n\n1st 128-bytes: Use by IOBDMA\n2nd 128-bytes: Reserved by kernel for scratch/TLS emulation.\n3rd 128-bytes: OCTEON-III LMTLINE\n\nNew config variable CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG provisions\nadditional lines, defaults to zero.\n\nSigned-off-by: David Daney <david.daney@cavium.com>\nSigned-off-by: Carlos Munoz <cmunoz@caviumnetworks.com>\n---\n arch/mips/cavium-octeon/Kconfig | 27 ++++++++++++--------\n arch/mips/cavium-octeon/setup.c | 16 ++++++------\n .../asm/mach-cavium-octeon/kernel-entry-init.h | 20 +++++++++------\n arch/mips/include/asm/mipsregs.h | 2 ++\n arch/mips/include/asm/octeon/octeon.h | 2 ++\n arch/mips/include/asm/processor.h | 2 +-\n arch/mips/kernel/octeon_switch.S | 2 --\n arch/mips/kernel/unaligned.c | 3 +++\n arch/mips/mm/tlbex.c | 29 ++++++----------------\n 9 files changed, 52 insertions(+), 51 deletions(-)", "diff": "diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig\nindex 211ef5b57214..fc6a1b44605b 100644\n--- a/arch/mips/cavium-octeon/Kconfig\n+++ b/arch/mips/cavium-octeon/Kconfig\n@@ -10,21 +10,26 @@ config CAVIUM_CN63XXP1\n \t non-CN63XXP1 hardware, so it is recommended to select \"n\"\n \t unless it is known the workarounds are needed.\n \n-config CAVIUM_OCTEON_CVMSEG_SIZE\n-\tint \"Number of L1 cache lines reserved for CVMSEG memory\"\n-\trange 0 54\n-\tdefault 1\n-\thelp\n-\t CVMSEG LM is a segment that accesses portions of the dcache as a\n-\t local memory; the larger CVMSEG is, the smaller the cache is.\n-\t This selects the size of CVMSEG LM, which is in cache blocks. The\n-\t legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is\n-\t between zero and 6192 bytes).\n-\n endif # CPU_CAVIUM_OCTEON\n \n if CAVIUM_OCTEON_SOC\n \n+config CAVIUM_OCTEON_EXTRA_CVMSEG\n+\tint \"Number of extra L1 cache lines reserved for CVMSEG memory\"\n+\trange 0 50\n+\tdefault 0\n+\thelp\n+\t CVMSEG LM is a segment that accesses portions of the dcache\n+\t as a local memory; the larger CVMSEG is, the smaller the\n+\t cache is. The kernel uses two or three blocks (one for TLB\n+\t exception handlers, one for driver IOBDMA operations, and on\n+\t models that need it, one for LMTDMA operations). This\n+\t selects an optional extra number of CVMSEG lines for use by\n+\t other software.\n+\n+\t Normally no extra lines are required, and this parameter\n+\t should be set to zero.\n+\n config CAVIUM_OCTEON_LOCK_L2\n \tbool \"Lock often used kernel code in the L2\"\n \tdefault \"y\"\ndiff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c\nindex 99e6a68bc652..51c4d3c3cada 100644\n--- a/arch/mips/cavium-octeon/setup.c\n+++ b/arch/mips/cavium-octeon/setup.c\n@@ -68,6 +68,12 @@ extern void pci_console_init(const char *arg);\n static unsigned long long max_memory = ULLONG_MAX;\n static unsigned long long reserve_low_mem;\n \n+/*\n+ * modified in hernel-entry-init.h, must have an initial value to keep\n+ * it from being clobbered when bss is zeroed.\n+ */\n+u32 octeon_cvmseg_lines = 2;\n+\n DEFINE_SEMAPHORE(octeon_bootbus_sem);\n EXPORT_SYMBOL(octeon_bootbus_sem);\n \n@@ -604,11 +610,7 @@ void octeon_user_io_init(void)\n \n \t/* R/W If set, CVMSEG is available for loads/stores in\n \t * kernel/debug mode. */\n-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0\n \tcvmmemctl.s.cvmsegenak = 1;\n-#else\n-\tcvmmemctl.s.cvmsegenak = 0;\n-#endif\n \tif (OCTEON_IS_OCTEON3()) {\n \t\t/* Enable LMTDMA */\n \t\tcvmmemctl.s.lmtena = 1;\n@@ -626,9 +628,9 @@ void octeon_user_io_init(void)\n \n \t/* Setup of CVMSEG is done in kernel-entry-init.h */\n \tif (smp_processor_id() == 0)\n-\t\tpr_notice(\"CVMSEG size: %d cache lines (%d bytes)\\n\",\n-\t\t\t CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,\n-\t\t\t CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);\n+\t\tpr_notice(\"CVMSEG size: %u cache lines (%u bytes)\\n\",\n+\t\t\t octeon_cvmseg_lines,\n+\t\t\t octeon_cvmseg_lines * 128);\n \n \tif (octeon_has_feature(OCTEON_FEATURE_FAU)) {\n \t\tunion cvmx_iob_fau_timeout fau_timeout;\ndiff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h\nindex c38b38ce5a3d..cdcca60978a2 100644\n--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h\n+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h\n@@ -26,11 +26,18 @@\n \t# a3 = address of boot descriptor block\n \t.set push\n \t.set arch=octeon\n+\tmfc0\tv1, CP0_PRID_REG\n+\tandi\tv1, 0xff00\n+\tli\tv0, 0x9500\t\t# cn78XX or later\n+\tsubu\tv1, v1, v0\n+\tli\tt2, 2 + CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG\n+\tbltz\tv1, 1f\n+\taddiu\tt2, 1\t\t\t# t2 has cvmseg_size\n+1:\n \t# Read the cavium mem control register\n \tdmfc0\tv0, CP0_CVMMEMCTL_REG\n \t# Clear the lower 6 bits, the CVMSEG size\n-\tdins\tv0, $0, 0, 6\n-\tori\tv0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE\n+\tdins\tv0, t2, 0, 6\n \tdmtc0\tv0, CP0_CVMMEMCTL_REG\t# Write the cavium mem control register\n \tdmfc0\tv0, CP0_CVMCTL_REG\t# Read the cavium control register\n \t# Disable unaligned load/store support but leave HW fixup enabled\n@@ -70,7 +77,7 @@\n \t# Flush dcache after config change\n \tcache\t9, 0($0)\n \t# Zero all of CVMSEG to make sure parity is correct\n-\tdli\tv0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE\n+\tmove\tv0, t2\n \tdsll\tv0, 7\n \tbeqz\tv0, 2f\n 1:\tdsubu\tv0, 8\n@@ -126,12 +133,7 @@\n \tLONG_L\tsp, (t0)\n \t# Set the SP global variable to zero so the master knows we've started\n \tLONG_S\tzero, (t0)\n-#ifdef __OCTEON__\n-\tsyncw\n-\tsyncw\n-#else\n \tsync\n-#endif\n \t# Jump to the normal Linux SMP entry point\n \tj smp_bootstrap\n \tnop\n@@ -148,6 +150,8 @@\n \n #endif /* CONFIG_SMP */\n octeon_main_processor:\n+\tdla\tv0, octeon_cvmseg_lines\n+\tsw\tt2, 0(v0)\n \t.set pop\n .endm\n \ndiff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h\nindex a6810923b3f0..df7654d7333d 100644\n--- a/arch/mips/include/asm/mipsregs.h\n+++ b/arch/mips/include/asm/mipsregs.h\n@@ -1126,6 +1126,8 @@\n #define FPU_CSR_RD\t0x3\t/* towards -Infinity */\n \n \n+#define CAVIUM_OCTEON_SCRATCH_OFFSET (2 * 128 - 16 - 32768)\n+\n #ifndef __ASSEMBLY__\n \n /*\ndiff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h\nindex d184592e6515..02eb194b2cdc 100644\n--- a/arch/mips/include/asm/octeon/octeon.h\n+++ b/arch/mips/include/asm/octeon/octeon.h\n@@ -392,6 +392,8 @@ static inline uint32_t octeon_npi_read32(uint64_t address)\n \n extern struct cvmx_bootinfo *octeon_bootinfo;\n \n+extern u32 octeon_cvmseg_lines;\n+\n extern uint64_t octeon_bootloader_entry_addr;\n \n extern void (*octeon_irq_setup_secondary)(void);\ndiff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h\nindex 95b8c471f572..3d264008afcb 100644\n--- a/arch/mips/include/asm/processor.h\n+++ b/arch/mips/include/asm/processor.h\n@@ -216,7 +216,7 @@ struct octeon_cop2_state {\n \t.cp2\t\t\t= {0,},\n \n struct octeon_cvmseg_state {\n-\tunsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]\n+\tunsigned long cvmseg[CONFIG_CAVIUM_OCTEON_EXTRA_CVMSEG + 3]\n \t\t\t [cpu_dcache_line_size() / sizeof(unsigned long)];\n };\n \ndiff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S\nindex e42113fe2762..4f56902d5ee7 100644\n--- a/arch/mips/kernel/octeon_switch.S\n+++ b/arch/mips/kernel/octeon_switch.S\n@@ -29,7 +29,6 @@\n \tcpu_save_nonscratch a0\n \tLONG_S\tra, THREAD_REG31(a0)\n \n-#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0\n \t/* Check if we need to store CVMSEG state */\n \tdmfc0\tt0, $11,7\t/* CvmMemCtl */\n \tbbit0\tt0, 6, 3f\t/* Is user access enabled? */\n@@ -58,7 +57,6 @@\n \tdmfc0\tt0, $11,7\t/* CvmMemCtl */\n \txori\tt0, t0, 0x40\t/* Bit 6 is CVMSEG user enable */\n \tdmtc0\tt0, $11,7\t/* CvmMemCtl */\n-#endif\n 3:\n \n #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)\ndiff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c\nindex 2d0b912f9e3e..610f9b4ccdae 100644\n--- a/arch/mips/kernel/unaligned.c\n+++ b/arch/mips/kernel/unaligned.c\n@@ -2281,6 +2281,9 @@ static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)\n \tforce_sig(SIGILL, current);\n }\n \n+#ifdef CONFIG_CPU_CAVIUM_OCTEON\n+#include <asm/octeon/octeon.h>\n+#endif\n asmlinkage void do_ade(struct pt_regs *regs)\n {\n \tenum ctx_state prev_state;\ndiff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c\nindex 79b9f2ad3ff5..3d3dfba465ae 100644\n--- a/arch/mips/mm/tlbex.c\n+++ b/arch/mips/mm/tlbex.c\n@@ -115,33 +115,17 @@ static int use_lwx_insns(void)\n \t\treturn 0;\n \t}\n }\n-#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \\\n- CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0\n-static bool scratchpad_available(void)\n-{\n-\treturn true;\n-}\n-static int scratchpad_offset(int i)\n-{\n-\t/*\n-\t * CVMSEG starts at address -32768 and extends for\n-\t * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines.\n-\t */\n-\ti += 1; /* Kernel use starts at the top and works down. */\n-\treturn CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768;\n-}\n-#else\n-static bool scratchpad_available(void)\n-{\n-\treturn false;\n-}\n+\n static int scratchpad_offset(int i)\n {\n+\tif (IS_ENABLED(CONFIG_CPU_CAVIUM_OCTEON))\n+\t\treturn (CAVIUM_OCTEON_SCRATCH_OFFSET - (8 * i));\n+\n \tBUG();\n \t/* Really unreachable, but evidently some GCC want this. */\n \treturn 0;\n }\n-#endif\n+\n /*\n * Found by experiment: At least some revisions of the 4kc throw under\n * some circumstances a machine check exception, triggered by invalid\n@@ -1302,7 +1286,8 @@ static void build_r4000_tlb_refill_handler(void)\n \tmemset(relocs, 0, sizeof(relocs));\n \tmemset(final_handler, 0, sizeof(final_handler));\n \n-\tif (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {\n+\tif (IS_ENABLED(CONFIG_64BIT) && use_bbit_insns() &&\n+\t (scratch_reg >= 0 || IS_ENABLED(CONFIG_CPU_CAVIUM_OCTEON))) {\n \t\thtlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,\n \t\t\t\t\t\t\t scratch_reg);\n \t\tvmalloc_mode = refill_scratch;\n", "prefixes": [ "5/7" ] }