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GET /api/1.2/patches/831249/?format=api
{ "id": 831249, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831249/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1509101470-7881-11-git-send-email-Dave.Martin@arm.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/1.2/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1509101470-7881-11-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-10-27T10:50:52", "name": "[v4,10/28] arm64/sve: Low-level CPU setup", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "953ae579331b9687ff3e9b111209196569ac8a7e", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/1.2/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1509101470-7881-11-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 10556, "url": "http://patchwork.ozlabs.org/api/1.2/series/10556/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/list/?series=10556", "date": "2017-10-27T10:50:43", "name": "ARM Scalable Vector Extension (SVE)", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/10556/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831249/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831249/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"LQwrF4tO\"; dkim-atps=neutral" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNgyr3nYwz9sNx\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tFri, 27 Oct 2017 22:05:40 +1100 (AEDT)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e82SI-00012Q-M3; Fri, 27 Oct 2017 11:05:38 +0000", "from foss.arm.com ([217.140.101.70])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e82F5-0003vr-Q0 for linux-arm-kernel@lists.infradead.org;\n\tFri, 27 Oct 2017 10:52:03 +0000", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 688981715;\n\tFri, 27 Oct 2017 03:51:39 -0700 (PDT)", "from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t89BE53F24A; Fri, 27 Oct 2017 03:51:37 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=iUHYWjQVJ3s9H6pMG196DSM0D5INkU8CvJgYw7pr6sA=;\n\tb=LQwrF4tOS+y0Ug\n\tJvKgi8vjISHuU8Xdy5HhURS22Cz7iI6ppDzhJ5WxDJVzLewdWVEPLJJ7ZiXP2Sqo/vLYXLUikap6u\n\t7kYb+34Nyffnew5BaKH6ZKfRNR9XhVY5jHXZkzu6Hrhn9COLISXd2PMYQoZKp096hZdA7OcXGZ+mU\n\tsbuM7HMG/geLPBG/q7rIOVpkLU8ANrfsM2HEf6mC9er8Uhz7GRzRSZeR5yKCh6TX2SHHpozeq76k9\n\tFm/DdRfQEU1B5zJ6Z4+pC7EUN2YCdKn0wiviFMIY6gfKZMherYSZ+iT8kOwmeSNDBLTYJNNG3m6xx\n\tfELIrB/7kxNbN5eiHshQ==;", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Subject": "[PATCH v4 10/28] arm64/sve: Low-level CPU setup", "Date": "Fri, 27 Oct 2017 11:50:52 +0100", "Message-Id": "<1509101470-7881-11-git-send-email-Dave.Martin@arm.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>", "References": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>", "MIME-Version": "1.0", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20171027_035200_170452_A7F376C6 ", "X-CRM114-Status": "UNSURE ( 9.01 )", "X-CRM114-Notice": "Please train this message.", "X-Spam-Score": "-6.9 (------)", "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Cc": "linux-arch@vger.kernel.org, Okamoto Takayuki <tokamoto@jp.fujitsu.com>,\n\tlibc-alpha@sourceware.org, Ard Biesheuvel <ard.biesheuvel@linaro.org>, \n\tSzabolcs Nagy <szabolcs.nagy@arm.com>, \n\tCatalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will.deacon@arm.com>, =?utf-8?q?Alex_Benn=C3=A9e?=\n\t<alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "To enable the kernel to use SVE, SVE traps from EL1 to EL2 must be\ndisabled. To take maximum advantage of the hardware, the full\navailable vector length also needs to be enabled for EL1 by\nprogramming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as\nrequired, but this cannot override the limit set by ZCR_EL2.)\n\nThis patch makes the appropriate changes to the EL2 early setup\ncode.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nCc: Alex Bennée <alex.bennee@linaro.org>\n\n---\n\n**Dropped at v3** Reviewed-by: Alex Bennée <alex.bennee@linaro.org>\n(Due to significant changes to the logic.)\n---\n arch/arm64/kernel/head.S | 13 ++++++++++++-\n 1 file changed, 12 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S\nindex cfa90a4..67e86a0 100644\n--- a/arch/arm64/kernel/head.S\n+++ b/arch/arm64/kernel/head.S\n@@ -524,8 +524,19 @@ CPU_LE(\tmovk\tx0, #0x30d0, lsl #16\t)\t// Clear EE and E0E on LE systems\n \tmov\tx0, #0x33ff\n \tmsr\tcptr_el2, x0\t\t\t// Disable copro. traps to EL2\n \n+\t/* SVE register access */\n+\tmrs\tx1, id_aa64pfr0_el1\n+\tubfx\tx1, x1, #ID_AA64PFR0_SVE_SHIFT, #4\n+\tcbz\tx1, 7f\n+\n+\tbic\tx0, x0, #CPTR_EL2_TZ\t\t// Also disable SVE traps\n+\tmsr\tcptr_el2, x0\t\t\t// Disable copro. traps to EL2\n+\tisb\n+\tmov\tx1, #ZCR_ELx_LEN_MASK\t\t// SVE: Enable full vector\n+\tmsr_s\tSYS_ZCR_EL2, x1\t\t\t// length for EL1.\n+\n \t/* Hypervisor stub */\n-\tadr_l\tx0, __hyp_stub_vectors\n+7:\tadr_l\tx0, __hyp_stub_vectors\n \tmsr\tvbar_el2, x0\n \n \t/* spsr */\n", "prefixes": [ "v4", "10/28" ] }