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GET /api/1.2/patches/831246/?format=api
{ "id": 831246, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831246/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1509101470-7881-8-git-send-email-Dave.Martin@arm.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/1.2/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1509101470-7881-8-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-10-27T10:50:49", "name": "[v4,07/28] arm64/sve: Low-level SVE architectural state manipulation functions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9ae6e830ca80793c9dffe5f7844dabf82692331f", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/1.2/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1509101470-7881-8-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 10556, "url": "http://patchwork.ozlabs.org/api/1.2/series/10556/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/list/?series=10556", "date": "2017-10-27T10:50:43", "name": "ARM Scalable Vector Extension (SVE)", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/10556/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831246/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831246/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"XFzmO6E2\"; dkim-atps=neutral" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNgw60fk9z9sNx\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tFri, 27 Oct 2017 22:03:18 +1100 (AEDT)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e82Pu-0006ll-VW; Fri, 27 Oct 2017 11:03:11 +0000", "from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]\n\thelo=foss.arm.com)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e82F5-0003vR-Py for linux-arm-kernel@lists.infradead.org;\n\tFri, 27 Oct 2017 10:52:15 +0000", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 895A216A0;\n\tFri, 27 Oct 2017 03:51:33 -0700 (PDT)", "from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com\n\t[10.72.51.249])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\tCA9973F24A; Fri, 27 Oct 2017 03:51:31 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=EzSOPAoa+FGRiZjIf+ibf8pPHB//Pz5QZqrJ6LWaSIk=;\n\tb=XFzmO6E2NGKY1A\n\t+J/YbVdtpF+5SJEN1ezWZ9mjMJSvVtIB1y4poMTYriF0CsHz7Fd4gA8pbr8fkc5K4iOYINvaGoiLB\n\tfggzVS1huwhRde3lenAdm5hzYyJ/0pbBNQllGYqfT3fV/tlE7BEXFd5XqDcqZcOC47TjcY0ZbEdQR\n\tD4dZr3MNtL0bUTqbLr54o5QjA8+Ac2qEOVeF8zVooHXQMMopHtuYg9R+ucxtbHmHJMzPRcOxrtaM2\n\tiP/FU6vUoXWRNK6Ex8loxaV4GD5E/V2guHPFA8nBjiQBtHB6ivwAj4go6u/jMoAb4v4kW9O6hpmVK\n\tc5Huu0YSKwtOQfOPo3tg==;", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Subject": "[PATCH v4 07/28] arm64/sve: Low-level SVE architectural state\n\tmanipulation functions", "Date": "Fri, 27 Oct 2017 11:50:49 +0100", "Message-Id": "<1509101470-7881-8-git-send-email-Dave.Martin@arm.com>", "X-Mailer": "git-send-email 2.1.4", "In-Reply-To": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>", "References": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>", "MIME-Version": "1.0", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20171027_035200_160908_1DBBB542 ", "X-CRM114-Status": "UNSURE ( 8.49 )", "X-CRM114-Notice": "Please train this message.", "X-Spam-Score": "-6.9 (------)", "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Cc": "linux-arch@vger.kernel.org, Okamoto Takayuki <tokamoto@jp.fujitsu.com>,\n\tlibc-alpha@sourceware.org, Ard Biesheuvel <ard.biesheuvel@linaro.org>, \n\tSzabolcs Nagy <szabolcs.nagy@arm.com>, \n\tCatalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will.deacon@arm.com>, =?utf-8?q?Alex_Benn=C3=A9e?=\n\t<alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "Manipulating the SVE architectural state, including the vector and\npredicate registers, first-fault register and the vector length,\nrequires the use of dedicated instructions added by SVE.\n\nThis patch adds suitable assembly functions for saving and\nrestoring the SVE registers and querying the vector length.\nSetting of the vector length is done as part of register restore.\n\nSince people building kernels may not all get an SVE-enabled\ntoolchain for a while, this patch uses macros that generate\nexplicit opcodes in place of assembler mnemonics.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nAcked-by: Catalin Marinas <catalin.marinas@arm.com>\n---\n arch/arm64/include/asm/fpsimd.h | 5 ++\n arch/arm64/include/asm/fpsimdmacros.h | 148 ++++++++++++++++++++++++++++++++++\n arch/arm64/kernel/entry-fpsimd.S | 17 ++++\n 3 files changed, 170 insertions(+)", "diff": "diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h\nindex 410c481..026a7c7 100644\n--- a/arch/arm64/include/asm/fpsimd.h\n+++ b/arch/arm64/include/asm/fpsimd.h\n@@ -67,6 +67,11 @@ extern void fpsimd_update_current_state(struct fpsimd_state *state);\n \n extern void fpsimd_flush_task_state(struct task_struct *target);\n \n+extern void sve_save_state(void *state, u32 *pfpsr);\n+extern void sve_load_state(void const *state, u32 const *pfpsr,\n+\t\t\t unsigned long vq_minus_1);\n+extern unsigned int sve_get_vl(void);\n+\n /* For use by EFI runtime services calls only */\n extern void __efi_fpsimd_begin(void);\n extern void __efi_fpsimd_end(void);\ndiff --git a/arch/arm64/include/asm/fpsimdmacros.h b/arch/arm64/include/asm/fpsimdmacros.h\nindex 0f5fdd3..e050d76 100644\n--- a/arch/arm64/include/asm/fpsimdmacros.h\n+++ b/arch/arm64/include/asm/fpsimdmacros.h\n@@ -75,3 +75,151 @@\n \tldr\tw\\tmpnr, [\\state, #16 * 2 + 4]\n \tfpsimd_restore_fpcr x\\tmpnr, \\state\n .endm\n+\n+/* Sanity-check macros to help avoid encoding garbage instructions */\n+\n+.macro _check_general_reg nr\n+\t.if (\\nr) < 0 || (\\nr) > 30\n+\t\t.error \"Bad register number \\nr.\"\n+\t.endif\n+.endm\n+\n+.macro _sve_check_zreg znr\n+\t.if (\\znr) < 0 || (\\znr) > 31\n+\t\t.error \"Bad Scalable Vector Extension vector register number \\znr.\"\n+\t.endif\n+.endm\n+\n+.macro _sve_check_preg pnr\n+\t.if (\\pnr) < 0 || (\\pnr) > 15\n+\t\t.error \"Bad Scalable Vector Extension predicate register number \\pnr.\"\n+\t.endif\n+.endm\n+\n+.macro _check_num n, min, max\n+\t.if (\\n) < (\\min) || (\\n) > (\\max)\n+\t\t.error \"Number \\n out of range [\\min,\\max]\"\n+\t.endif\n+.endm\n+\n+/* SVE instruction encodings for non-SVE-capable assemblers */\n+\n+/* STR (vector): STR Z\\nz, [X\\nxbase, #\\offset, MUL VL] */\n+.macro _sve_str_v nz, nxbase, offset=0\n+\t_sve_check_zreg \\nz\n+\t_check_general_reg \\nxbase\n+\t_check_num (\\offset), -0x100, 0xff\n+\t.inst\t0xe5804000\t\t\t\\\n+\t\t| (\\nz)\t\t\t\t\\\n+\t\t| ((\\nxbase) << 5)\t\t\\\n+\t\t| (((\\offset) & 7) << 10)\t\\\n+\t\t| (((\\offset) & 0x1f8) << 13)\n+.endm\n+\n+/* LDR (vector): LDR Z\\nz, [X\\nxbase, #\\offset, MUL VL] */\n+.macro _sve_ldr_v nz, nxbase, offset=0\n+\t_sve_check_zreg \\nz\n+\t_check_general_reg \\nxbase\n+\t_check_num (\\offset), -0x100, 0xff\n+\t.inst\t0x85804000\t\t\t\\\n+\t\t| (\\nz)\t\t\t\t\\\n+\t\t| ((\\nxbase) << 5)\t\t\\\n+\t\t| (((\\offset) & 7) << 10)\t\\\n+\t\t| (((\\offset) & 0x1f8) << 13)\n+.endm\n+\n+/* STR (predicate): STR P\\np, [X\\nxbase, #\\offset, MUL VL] */\n+.macro _sve_str_p np, nxbase, offset=0\n+\t_sve_check_preg \\np\n+\t_check_general_reg \\nxbase\n+\t_check_num (\\offset), -0x100, 0xff\n+\t.inst\t0xe5800000\t\t\t\\\n+\t\t| (\\np)\t\t\t\t\\\n+\t\t| ((\\nxbase) << 5)\t\t\\\n+\t\t| (((\\offset) & 7) << 10)\t\\\n+\t\t| (((\\offset) & 0x1f8) << 13)\n+.endm\n+\n+/* LDR (predicate): LDR P\\np, [X\\nxbase, #\\offset, MUL VL] */\n+.macro _sve_ldr_p np, nxbase, offset=0\n+\t_sve_check_preg \\np\n+\t_check_general_reg \\nxbase\n+\t_check_num (\\offset), -0x100, 0xff\n+\t.inst\t0x85800000\t\t\t\\\n+\t\t| (\\np)\t\t\t\t\\\n+\t\t| ((\\nxbase) << 5)\t\t\\\n+\t\t| (((\\offset) & 7) << 10)\t\\\n+\t\t| (((\\offset) & 0x1f8) << 13)\n+.endm\n+\n+/* RDVL X\\nx, #\\imm */\n+.macro _sve_rdvl nx, imm\n+\t_check_general_reg \\nx\n+\t_check_num (\\imm), -0x20, 0x1f\n+\t.inst\t0x04bf5000\t\t\t\\\n+\t\t| (\\nx)\t\t\t\t\\\n+\t\t| (((\\imm) & 0x3f) << 5)\n+.endm\n+\n+/* RDFFR (unpredicated): RDFFR P\\np.B */\n+.macro _sve_rdffr np\n+\t_sve_check_preg \\np\n+\t.inst\t0x2519f000\t\t\t\\\n+\t\t| (\\np)\n+.endm\n+\n+/* WRFFR P\\np.B */\n+.macro _sve_wrffr np\n+\t_sve_check_preg \\np\n+\t.inst\t0x25289000\t\t\t\\\n+\t\t| ((\\np) << 5)\n+.endm\n+\n+.macro __for from:req, to:req\n+\t.if (\\from) == (\\to)\n+\t\t_for__body \\from\n+\t.else\n+\t\t__for \\from, (\\from) + ((\\to) - (\\from)) / 2\n+\t\t__for (\\from) + ((\\to) - (\\from)) / 2 + 1, \\to\n+\t.endif\n+.endm\n+\n+.macro _for var:req, from:req, to:req, insn:vararg\n+\t.macro _for__body \\var:req\n+\t\t\\insn\n+\t.endm\n+\n+\t__for \\from, \\to\n+\n+\t.purgem _for__body\n+.endm\n+\n+.macro sve_save nxbase, xpfpsr, nxtmp\n+ _for n, 0, 31,\t_sve_str_v\t\\n, \\nxbase, \\n - 34\n+ _for n, 0, 15,\t_sve_str_p\t\\n, \\nxbase, \\n - 16\n+\t\t_sve_rdffr\t0\n+\t\t_sve_str_p\t0, \\nxbase\n+\t\t_sve_ldr_p\t0, \\nxbase, -16\n+\n+\t\tmrs\t\tx\\nxtmp, fpsr\n+\t\tstr\t\tw\\nxtmp, [\\xpfpsr]\n+\t\tmrs\t\tx\\nxtmp, fpcr\n+\t\tstr\t\tw\\nxtmp, [\\xpfpsr, #4]\n+.endm\n+\n+.macro sve_load nxbase, xpfpsr, xvqminus1, nxtmp\n+\t\tmrs_s\t\tx\\nxtmp, SYS_ZCR_EL1\n+\t\tbic\t\tx\\nxtmp, x\\nxtmp, ZCR_ELx_LEN_MASK\n+\t\torr\t\tx\\nxtmp, x\\nxtmp, \\xvqminus1\n+\t\tmsr_s\t\tSYS_ZCR_EL1, x\\nxtmp\t// self-synchronising\n+\n+ _for n, 0, 31,\t_sve_ldr_v\t\\n, \\nxbase, \\n - 34\n+\t\t_sve_ldr_p\t0, \\nxbase\n+\t\t_sve_wrffr\t0\n+ _for n, 0, 15,\t_sve_ldr_p\t\\n, \\nxbase, \\n - 16\n+\n+\t\tldr\t\tw\\nxtmp, [\\xpfpsr]\n+\t\tmsr\t\tfpsr, x\\nxtmp\n+\t\tldr\t\tw\\nxtmp, [\\xpfpsr, #4]\n+\t\tmsr\t\tfpcr, x\\nxtmp\n+.endm\ndiff --git a/arch/arm64/kernel/entry-fpsimd.S b/arch/arm64/kernel/entry-fpsimd.S\nindex 6a27cd6..73f17bf 100644\n--- a/arch/arm64/kernel/entry-fpsimd.S\n+++ b/arch/arm64/kernel/entry-fpsimd.S\n@@ -41,3 +41,20 @@ ENTRY(fpsimd_load_state)\n \tfpsimd_restore x0, 8\n \tret\n ENDPROC(fpsimd_load_state)\n+\n+#ifdef CONFIG_ARM64_SVE\n+ENTRY(sve_save_state)\n+\tsve_save 0, x1, 2\n+\tret\n+ENDPROC(sve_save_state)\n+\n+ENTRY(sve_load_state)\n+\tsve_load 0, x1, x2, 3\n+\tret\n+ENDPROC(sve_load_state)\n+\n+ENTRY(sve_get_vl)\n+\t_sve_rdvl\t0, 1\n+\tret\n+ENDPROC(sve_get_vl)\n+#endif /* CONFIG_ARM64_SVE */\n", "prefixes": [ "v4", "07/28" ] }