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GET /api/1.2/patches/831235/?format=api
{ "id": 831235, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831235/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-26-git-send-email-Dave.Martin@arm.com/", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/1.2/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1509101470-7881-26-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-10-27T10:51:07", "name": "[v4,25/28] arm64/sve: Detect SVE and activate runtime support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4cde1dd660a70602adaddf6cf1b1cdc2919019f4", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/1.2/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-26-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 10555, "url": "http://patchwork.ozlabs.org/api/1.2/series/10555/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=10555", "date": "2017-10-27T10:50:42", "name": "ARM Scalable Vector Extension (SVE)", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/10555/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831235/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831235/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<libc-alpha-return-86467-incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list libc-alpha@sourceware.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-86467-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"wiPYCQHN\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNglz1cV9z9rxj\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 27 Oct 2017 21:56:15 +1100 (AEDT)", "(qmail 121450 invoked by alias); 27 Oct 2017 10:52:12 -0000", "(qmail 121393 invoked by uid 89); 27 Oct 2017 10:52:11 -0000" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references; q=dns; s=default; b=dmlruG4gcGl/HRRhU87jEpFeKK9WINM\n\t+Ota5V1CThvbL2VGZ3uIfEyyBb/X1jrpOIX/aXNkXh7RrEboErvJDpBhpqByqOXC\n\tUQcgUIqRkHagx6QXi/vUsSaNElZrTzEZSHcNIoVogmgMA+7Pbl0R3mSw7fMEAzvn\n\tcbF1Y0mGvkQQ=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references; s=default; bh=AsJ6JjrtpMWtFf89wbWsDBQGyfs=; b=wiPYC\n\tQHNS2JqjlhIPqMXtxTAvzyTFshVtSr/1A5mYk/ZRJIdVLJ9WUe1JOYLS1PleKjO/\n\tofMPtsMuglveHZv5iGAVje4ai0EJk4gSrv72JbpRpoQq27mYN4E0cbJdUktjbS9J\n\tV/bOCM13iAIQQ/1z1eN5kmrx34jvvkMf50p28Q=", "Mailing-List": "contact libc-alpha-help@sourceware.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<libc-alpha.sourceware.org>", "List-Unsubscribe": "<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>", "List-Subscribe": "<mailto:libc-alpha-subscribe@sourceware.org>", "List-Archive": "<http://sourceware.org/ml/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>", "Sender": "libc-alpha-owner@sourceware.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-26.1 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS,\n\tRP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=", "X-HELO": "foss.arm.com", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Cc": "Catalin Marinas <catalin.marinas@arm.com>, Will Deacon\n\t<will.deacon@arm.com>, \tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= <alex.bennee@linaro.org>,\n\tSzabolcs Nagy <szabolcs.nagy@arm.com>, Okamoto Takayuki\n\t<tokamoto@jp.fujitsu.com>, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org", "Subject": "[PATCH v4 25/28] arm64/sve: Detect SVE and activate runtime support", "Date": "Fri, 27 Oct 2017 11:51:07 +0100", "Message-Id": "<1509101470-7881-26-git-send-email-Dave.Martin@arm.com>", "In-Reply-To": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>", "References": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>" }, "content": "This patch enables detection of hardware SVE support via the\ncpufeatures framework, and reports its presence to the kernel and\nuserspace via the new ARM64_SVE cpucap and HWCAP_SVE hwcap\nrespectively.\n\nUserspace can also detect SVE using ID_AA64PFR0_EL1, using the\ncpufeatures MRS emulation.\n\nWhen running on hardware that supports SVE, this enables runtime\nkernel support for SVE, and allows user tasks to execute SVE\ninstructions and make of the of the SVE-specific user/kernel\ninterface extensions implemented by this series.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nReviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>\nCc: Catalin Marinas <catalin.marinas@arm.com>\n\n---\n\n**Dropped** Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nThe entry.S changes need reviewing; however the rest of the cpufeatures\nsupport (reviewed by Suzuki) has not changed and shouldn't need re-\nreview.\n\nChanges since v3\n----------------\n\nChanges requested by Catalin Marinas / Will Deacon:\n\n * ABI change: Zero SVE regs on syscall entry:\n\n Move to asm alternatives for skipping SVE discard at syscall entry,\n now that we have a suitable cpucap defined.\n\nMiscellaneous:\n\n * Add HWCAP_SVE description to elf_hwcaps.txt\n---\n Documentation/arm64/cpu-feature-registers.txt | 6 +++++-\n Documentation/arm64/elf_hwcaps.txt | 4 ++++\n arch/arm64/include/asm/cpucaps.h | 3 ++-\n arch/arm64/include/asm/cpufeature.h | 3 ++-\n arch/arm64/include/uapi/asm/hwcap.h | 1 +\n arch/arm64/kernel/cpufeature.c | 17 +++++++++++++++++\n arch/arm64/kernel/cpuinfo.c | 1 +\n arch/arm64/kernel/entry.S | 7 ++++---\n 8 files changed, 36 insertions(+), 6 deletions(-)", "diff": "diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt\nindex 011ddfc..bd9b3fa 100644\n--- a/Documentation/arm64/cpu-feature-registers.txt\n+++ b/Documentation/arm64/cpu-feature-registers.txt\n@@ -142,7 +142,11 @@ infrastructure:\n x--------------------------------------------------x\n | Name | bits | visible |\n |--------------------------------------------------|\n- | RES0 | [63-28] | n |\n+ | RES0 | [63-36] | n |\n+ |--------------------------------------------------|\n+ | SVE | [35-32] | y |\n+ |--------------------------------------------------|\n+ | RES0 | [31-28] | n |\n |--------------------------------------------------|\n | GIC | [27-24] | n |\n |--------------------------------------------------|\ndiff --git a/Documentation/arm64/elf_hwcaps.txt b/Documentation/arm64/elf_hwcaps.txt\nindex 0ba1805..89edba1 100644\n--- a/Documentation/arm64/elf_hwcaps.txt\n+++ b/Documentation/arm64/elf_hwcaps.txt\n@@ -154,3 +154,7 @@ HWCAP_ASIMDDP\n HWCAP_SHA512\n \n Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0002.\n+\n+HWCAP_SVE\n+\n+ Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001.\ndiff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h\nindex 8da6216..2ff7c5e 100644\n--- a/arch/arm64/include/asm/cpucaps.h\n+++ b/arch/arm64/include/asm/cpucaps.h\n@@ -40,7 +40,8 @@\n #define ARM64_WORKAROUND_858921\t\t\t19\n #define ARM64_WORKAROUND_CAVIUM_30115\t\t20\n #define ARM64_HAS_DCPOP\t\t\t\t21\n+#define ARM64_SVE\t\t\t\t22\n \n-#define ARM64_NCAPS\t\t\t\t22\n+#define ARM64_NCAPS\t\t\t\t23\n \n #endif /* __ASM_CPUCAPS_H */\ndiff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h\nindex 9b27e8c..ac67cfc 100644\n--- a/arch/arm64/include/asm/cpufeature.h\n+++ b/arch/arm64/include/asm/cpufeature.h\n@@ -273,7 +273,8 @@ static inline bool system_uses_ttbr0_pan(void)\n \n static inline bool system_supports_sve(void)\n {\n-\treturn false;\n+\treturn IS_ENABLED(CONFIG_ARM64_SVE) &&\n+\t\tcpus_have_const_cap(ARM64_SVE);\n }\n \n /*\ndiff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h\nindex a4bad90..6229410 100644\n--- a/arch/arm64/include/uapi/asm/hwcap.h\n+++ b/arch/arm64/include/uapi/asm/hwcap.h\n@@ -41,5 +41,6 @@\n #define HWCAP_SM4\t\t(1 << 19)\n #define HWCAP_ASIMDDP\t\t(1 << 20)\n #define HWCAP_SHA512\t\t(1 << 21)\n+#define HWCAP_SVE\t\t(1 << 22)\n \n #endif /* _UAPI__ASM_HWCAP_H */\ndiff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c\nindex 2154373..c5ba009 100644\n--- a/arch/arm64/kernel/cpufeature.c\n+++ b/arch/arm64/kernel/cpufeature.c\n@@ -145,6 +145,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {\n };\n \n static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {\n+\tARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),\n \tARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),\n \tS_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),\n \tS_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),\n@@ -948,6 +949,19 @@ static const struct arm64_cpu_capabilities arm64_features[] = {\n \t\t.min_field_value = 1,\n \t},\n #endif\n+#ifdef CONFIG_ARM64_SVE\n+\t{\n+\t\t.desc = \"Scalable Vector Extension\",\n+\t\t.capability = ARM64_SVE,\n+\t\t.def_scope = SCOPE_SYSTEM,\n+\t\t.sys_reg = SYS_ID_AA64PFR0_EL1,\n+\t\t.sign = FTR_UNSIGNED,\n+\t\t.field_pos = ID_AA64PFR0_SVE_SHIFT,\n+\t\t.min_field_value = ID_AA64PFR0_SVE,\n+\t\t.matches = has_cpuid_feature,\n+\t\t.enable = sve_kernel_enable,\n+\t},\n+#endif /* CONFIG_ARM64_SVE */\n \t{},\n };\n \n@@ -985,6 +999,9 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {\n \tHWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),\n \tHWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),\n \tHWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),\n+#ifdef CONFIG_ARM64_SVE\n+\tHWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),\n+#endif\n \t{},\n };\n \ndiff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c\nindex 58da504..1e25545 100644\n--- a/arch/arm64/kernel/cpuinfo.c\n+++ b/arch/arm64/kernel/cpuinfo.c\n@@ -75,6 +75,7 @@ static const char *const hwcap_str[] = {\n \t\"sm4\",\n \t\"asimddp\",\n \t\"sha512\",\n+\t\"sve\",\n \tNULL\n };\n \ndiff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S\nindex 56e848f..67522ac 100644\n--- a/arch/arm64/kernel/entry.S\n+++ b/arch/arm64/kernel/entry.S\n@@ -853,9 +853,10 @@ el0_svc:\n \tmov\twscno, w8\t\t\t// syscall number in w8\n \tmov\twsc_nr, #__NR_syscalls\n \n-#ifndef CONFIG_ARM64_SVE\n+#ifdef CONFIG_ARM64_SVE\n+alternative_if_not ARM64_SVE\n \tb\tel0_svc_naked\n-#else\n+alternative_else_nop_endif\n \ttbz\tx16, #TIF_SVE, el0_svc_naked\t// Skip unless TIF_SVE set:\n \tbic\tx16, x16, #_TIF_SVE\t\t// discard SVE state\n \tstr\tx16, [tsk, #TSK_TI_FLAGS]\n@@ -870,7 +871,7 @@ el0_svc:\n \tmrs\tx9, cpacr_el1\n \tbic\tx9, x9, #CPACR_EL1_ZEN_EL0EN\t// disable SVE for el0\n \tmsr\tcpacr_el1, x9\t\t\t// synchronised by eret to el0\n-#endif /* CONFIG_ARM64_SVE */\n+#endif\n \n el0_svc_naked:\t\t\t\t\t// compat entry point\n \tstp\tx0, xscno, [sp, #S_ORIG_X0]\t// save the original x0 and syscall number\n", "prefixes": [ "v4", "25/28" ] }