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GET /api/1.2/patches/831229/?format=api
{ "id": 831229, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831229/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-22-git-send-email-Dave.Martin@arm.com/", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/1.2/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1509101470-7881-22-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-10-27T10:51:03", "name": "[v4,21/28] arm64/sve: Add sysctl to set the default vector length for new processes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e8875bb4ea2644807c3e083ad8e3e8cd2a08290e", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/1.2/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-22-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 10555, "url": "http://patchwork.ozlabs.org/api/1.2/series/10555/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=10555", "date": "2017-10-27T10:50:42", "name": "ARM Scalable Vector Extension (SVE)", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/10555/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831229/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831229/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<libc-alpha-return-86463-incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list libc-alpha@sourceware.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-86463-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"HCApGT3O\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNglH3T8Lz9sNx\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 27 Oct 2017 21:55:39 +1100 (AEDT)", "(qmail 120405 invoked by alias); 27 Oct 2017 10:52:04 -0000", "(qmail 120351 invoked by uid 89); 27 Oct 2017 10:52:03 -0000" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=e+TkyGAYML551Lvw6BTFC6UuhsrHfFnMlNyaPF+666o\n\tb7VM+T1T3gjqByCHzY2/j/h7vcVBKHeLTd3Bkr3bdkPChs5YmXSt7811ncoGkmC+\n\t0L8rfF90fYA+YaHSCbcrkarUs9EQsYoJVsGrmstfx7+41k8Ynw9gdmrvsoNAYlK0\n\t=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=54EFGulEJiDv5TwHKG+xG0N4Bzo=; b=HCApGT3OISzF2ZNCK\n\tWtoAie+33xw10osycxaxS71BRqtOCSk80oAlJc8XwuBIik6mAIuyREB55vLLPpY9\n\t5uMK2INwCcPo9uEaq62TwlxI6zDE12385amzyuvu6QUZs8dsXzWDxucjH7ibzNk+\n\tihkdrhuyDn5d+i+EUh5GaJaJRE=", "Mailing-List": "contact libc-alpha-help@sourceware.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<libc-alpha.sourceware.org>", "List-Unsubscribe": "<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>", "List-Subscribe": "<mailto:libc-alpha-subscribe@sourceware.org>", "List-Archive": "<http://sourceware.org/ml/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>", "Sender": "libc-alpha-owner@sourceware.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=Writing", "X-HELO": "foss.arm.com", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Cc": "Catalin Marinas <catalin.marinas@arm.com>, Will Deacon\n\t<will.deacon@arm.com>, \tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= <alex.bennee@linaro.org>,\n\tSzabolcs Nagy <szabolcs.nagy@arm.com>, Okamoto Takayuki\n\t<tokamoto@jp.fujitsu.com>, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org", "Subject": "[PATCH v4 21/28] arm64/sve: Add sysctl to set the default vector\n\tlength for new processes", "Date": "Fri, 27 Oct 2017 11:51:03 +0100", "Message-Id": "<1509101470-7881-22-git-send-email-Dave.Martin@arm.com>", "In-Reply-To": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>", "References": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit" }, "content": "Because of the effect of SVE on the size of the signal frame, the\ndefault vector length used for new processes involves a tradeoff\nbetween performance of SVE-enabled software on the one hand, and\nreliability of non-SVE-aware software on the other hand.\n\nFor this reason, the best choice depends on the repertoire of\nuserspace software in use and is thus best left up to distro\nmaintainers, sysadmins and developers.\n\nIf CONFIG_SYSCTL and CONFIG_PROC_SYSCTL are enabled, this patch\nexposes the default vector length in\n/proc/sys/abi/sve_default_vector_length, where boot scripts or the\nadventurous can poke it.\n\nIn common with other arm64 ABI sysctls, this control is currently\nglobal: setting it requires CAP_SYS_ADMIN in the root user\nnamespace, but the value set is effective for subsequent execs in\nall namespaces. The control only affects _new_ processes, however:\nchanging it does not affect the vector length of any existing\nprocess.\n\nThe intended usage model is that if userspace is known to be fully\nSVE-tolerant (or a developer is curious to find out) then this\nparameter can be cranked up during system startup.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\n---\n arch/arm64/kernel/fpsimd.c | 62 +++++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 61 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\nindex 7465622..f9d3287 100644\n--- a/arch/arm64/kernel/fpsimd.c\n+++ b/arch/arm64/kernel/fpsimd.c\n@@ -35,6 +35,7 @@\n #include <linux/sched/signal.h>\n #include <linux/signal.h>\n #include <linux/slab.h>\n+#include <linux/sysctl.h>\n \n #include <asm/fpsimd.h>\n #include <asm/cputype.h>\n@@ -333,6 +334,65 @@ static unsigned int find_supported_vector_length(unsigned int vl)\n \treturn sve_vl_from_vq(bit_to_vq(bit));\n }\n \n+#ifdef CONFIG_SYSCTL\n+\n+static int sve_proc_do_default_vl(struct ctl_table *table, int write,\n+\t\t\t\t void __user *buffer, size_t *lenp,\n+\t\t\t\t loff_t *ppos)\n+{\n+\tint ret;\n+\tint vl = sve_default_vl;\n+\tstruct ctl_table tmp_table = {\n+\t\t.data = &vl,\n+\t\t.maxlen = sizeof(vl),\n+\t};\n+\n+\tret = proc_dointvec(&tmp_table, write, buffer, lenp, ppos);\n+\tif (ret || !write)\n+\t\treturn ret;\n+\n+\t/* Writing -1 has the special meaning \"set to max\": */\n+\tif (vl == -1) {\n+\t\t/* Fail safe if sve_max_vl wasn't initialised */\n+\t\tif (WARN_ON(!sve_vl_valid(sve_max_vl)))\n+\t\t\tvl = SVE_VL_MIN;\n+\t\telse\n+\t\t\tvl = sve_max_vl;\n+\n+\t\tgoto chosen;\n+\t}\n+\n+\tif (!sve_vl_valid(vl))\n+\t\treturn -EINVAL;\n+\n+\tvl = find_supported_vector_length(vl);\n+chosen:\n+\tsve_default_vl = vl;\n+\treturn 0;\n+}\n+\n+static struct ctl_table sve_default_vl_table[] = {\n+\t{\n+\t\t.procname\t= \"sve_default_vector_length\",\n+\t\t.mode\t\t= 0644,\n+\t\t.proc_handler\t= sve_proc_do_default_vl,\n+\t},\n+\t{ }\n+};\n+\n+static int __init sve_sysctl_init(void)\n+{\n+\tif (system_supports_sve())\n+\t\tif (!register_sysctl(\"abi\", sve_default_vl_table))\n+\t\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+#else /* ! CONFIG_SYSCTL */\n+static int __init sve_sysctl_init(void) { return 0; }\n+#endif /* ! CONFIG_SYSCTL */\n+\n #define ZREG(sve_state, vq, n) ((char *)(sve_state) +\t\t\\\n \t(SVE_SIG_ZREG_OFFSET(vq, n) - SVE_SIG_REGS_OFFSET))\n \n@@ -1207,6 +1267,6 @@ static int __init fpsimd_init(void)\n \tif (!(elf_hwcap & HWCAP_ASIMD))\n \t\tpr_notice(\"Advanced SIMD is not implemented\\n\");\n \n-\treturn 0;\n+\treturn sve_sysctl_init();\n }\n core_initcall(fpsimd_init);\n", "prefixes": [ "v4", "21/28" ] }