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GET /api/1.2/patches/831214/?format=api
{ "id": 831214, "url": "http://patchwork.ozlabs.org/api/1.2/patches/831214/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-13-git-send-email-Dave.Martin@arm.com/", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/1.2/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1509101470-7881-13-git-send-email-Dave.Martin@arm.com>", "list_archive_url": null, "date": "2017-10-27T10:50:54", "name": "[v4,12/28] arm64/sve: Support vector length resetting for new processes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e147500ea79a0cda57e50b261586dcfd9ca04027", "submitter": { "id": 26612, "url": "http://patchwork.ozlabs.org/api/1.2/people/26612/?format=api", "name": "Dave Martin", "email": "Dave.Martin@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/1509101470-7881-13-git-send-email-Dave.Martin@arm.com/mbox/", "series": [ { "id": 10555, "url": "http://patchwork.ozlabs.org/api/1.2/series/10555/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=10555", "date": "2017-10-27T10:50:42", "name": "ARM Scalable Vector Extension (SVE)", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/10555/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/831214/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/831214/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<libc-alpha-return-86453-incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "mailing list libc-alpha@sourceware.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-86453-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"Dc8Xa53t\"; dkim-atps=neutral", "sourceware.org; auth=none" ], "Received": [ "from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNgj15Vh9z9sNx\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 27 Oct 2017 21:53:41 +1100 (AEDT)", "(qmail 118171 invoked by alias); 27 Oct 2017 10:51:46 -0000", "(qmail 118130 invoked by uid 89); 27 Oct 2017 10:51:46 -0000" ], "DomainKey-Signature": "a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=PjDvU/HWu0vmZMUSmnyI6Qxe0wdMVF4fjBqf8MZTuU+\n\tdOGH4pbiazuDQj8nss6/ZuMtT4WR32pXdZx0oOuOwodkpa718TiUUAYZHikiCe78\n\t3mBD44ifRzMyLKETAJft8Ots0sAqH7ksLQWz9ikF7TTu9ngMGcLQzOBWr6VngF0k\n\t=", "DKIM-Signature": "v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=bu49Pvp46Ifj+MtSs8NJoXK64Mo=; b=Dc8Xa53tz06Ajgwrj\n\tHaTV1ww6iQQMtgoOLDI6/bCO3pNc7MvMqRfWas01qU9uvuBDDFXjLa4DSL5ZkK7i\n\tf22lYurs0bEcOL3Mo7xGAtJbt4jrM+Fq+v9zWP7sVj+acGkBk6hTHCBVmEdRmftO\n\tQrcIu+hg/NRrgJnJsxp0fdlsp0=", "Mailing-List": "contact libc-alpha-help@sourceware.org; run by ezmlm", "Precedence": "bulk", "List-Id": "<libc-alpha.sourceware.org>", "List-Unsubscribe": "<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>", "List-Subscribe": "<mailto:libc-alpha-subscribe@sourceware.org>", "List-Archive": "<http://sourceware.org/ml/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>", "Sender": "libc-alpha-owner@sourceware.org", "X-Virus-Found": "No", "X-Spam-SWARE-Status": "No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=scheduled, Inherit,\n\tSubsequent", "X-HELO": "foss.arm.com", "From": "Dave Martin <Dave.Martin@arm.com>", "To": "linux-arm-kernel@lists.infradead.org", "Cc": "Catalin Marinas <catalin.marinas@arm.com>, Will Deacon\n\t<will.deacon@arm.com>, \tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= <alex.bennee@linaro.org>,\n\tSzabolcs Nagy <szabolcs.nagy@arm.com>, Okamoto Takayuki\n\t<tokamoto@jp.fujitsu.com>, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org", "Subject": "[PATCH v4 12/28] arm64/sve: Support vector length resetting for new\n\tprocesses", "Date": "Fri, 27 Oct 2017 11:50:54 +0100", "Message-Id": "<1509101470-7881-13-git-send-email-Dave.Martin@arm.com>", "In-Reply-To": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>", "References": "<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit" }, "content": "It's desirable to be able to reset the vector length to some sane\ndefault for new processes, since the new binary and its libraries\nmay or may not be SVE-aware.\n\nThis patch tracks the desired post-exec vector length (if any) in a\nnew thread member sve_vl_onexec, and adds a new thread flag\nTIF_SVE_VL_INHERIT to control whether to inherit or reset the\nvector length. Currently these are inactive. Subsequent patches\nwill provide the capability to configure them.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\n---\n arch/arm64/include/asm/processor.h | 1 +\n arch/arm64/include/asm/thread_info.h | 1 +\n arch/arm64/kernel/fpsimd.c | 16 ++++++++++++----\n 3 files changed, 14 insertions(+), 4 deletions(-)", "diff": "diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h\nindex e2f575d..c6fddb0 100644\n--- a/arch/arm64/include/asm/processor.h\n+++ b/arch/arm64/include/asm/processor.h\n@@ -107,6 +107,7 @@ struct thread_struct {\n \tstruct fpsimd_state\tfpsimd_state;\n \tvoid\t\t\t*sve_state;\t/* SVE registers, if any */\n \tunsigned int\t\tsve_vl;\t\t/* SVE vector length */\n+\tunsigned int\t\tsve_vl_onexec;\t/* SVE vl after next exec */\n \tunsigned long\t\tfault_address;\t/* fault info */\n \tunsigned long\t\tfault_code;\t/* ESR_EL1 value */\n \tstruct debug_info\tdebug;\t\t/* debugging */\ndiff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h\nindex 92b7b48..eb43128 100644\n--- a/arch/arm64/include/asm/thread_info.h\n+++ b/arch/arm64/include/asm/thread_info.h\n@@ -95,6 +95,7 @@ void arch_release_task_struct(struct task_struct *tsk);\n #define TIF_SINGLESTEP\t\t21\n #define TIF_32BIT\t\t22\t/* 32bit process */\n #define TIF_SVE\t\t\t23\t/* Scalable Vector Extension in use */\n+#define TIF_SVE_VL_INHERIT\t24\t/* Inherit sve_vl_onexec across exec */\n \n #define _TIF_SIGPENDING\t\t(1 << TIF_SIGPENDING)\n #define _TIF_NEED_RESCHED\t(1 << TIF_NEED_RESCHED)\ndiff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\nindex 0b15a594..2b691d1 100644\n--- a/arch/arm64/kernel/fpsimd.c\n+++ b/arch/arm64/kernel/fpsimd.c\n@@ -109,6 +109,9 @@\n */\n static DEFINE_PER_CPU(struct fpsimd_state *, fpsimd_last_state);\n \n+/* Default VL for tasks that don't set it explicitly: */\n+static int sve_default_vl = SVE_VL_MIN;\n+\n /*\n * Call __sve_free() directly only if you know task can't be scheduled\n * or preempted.\n@@ -472,15 +475,20 @@ void fpsimd_flush_thread(void)\n \t\t * If a bug causes this to go wrong, we make some noise and\n \t\t * try to fudge thread.sve_vl to a safe value here.\n \t\t */\n-\t\tvl = current->thread.sve_vl;\n-\n-\t\tif (vl == 0)\n-\t\t\tvl = SVE_VL_MIN;\n+\t\tvl = current->thread.sve_vl_onexec ?\n+\t\t\tcurrent->thread.sve_vl_onexec : sve_default_vl;\n \n \t\tif (WARN_ON(!sve_vl_valid(vl)))\n \t\t\tvl = SVE_VL_MIN;\n \n \t\tcurrent->thread.sve_vl = vl;\n+\n+\t\t/*\n+\t\t * If the task is not set to inherit, ensure that the vector\n+\t\t * length will be reset by a subsequent exec:\n+\t\t */\n+\t\tif (!test_thread_flag(TIF_SVE_VL_INHERIT))\n+\t\t\tcurrent->thread.sve_vl_onexec = 0;\n \t}\n \n \tset_thread_flag(TIF_FOREIGN_FPSTATE);\n", "prefixes": [ "v4", "12/28" ] }